PUBLICATIONS

Prof. Raimund Ubar,
Tallinn Technical University,
Raja tee 15, Tallinn 12618, Estonia
Tel. (+372) 620 22 52
FAX  (+37) 620 22 53
E-mail: raiub@pld.ttu.ee

Books:

  1. O.Novak, E.Gramatova, R.Ubar. Handbook of Electronic Testing. CTU Printhouse, Prague, 2005, 400 p.
  2. R.Ubar. Diagnostics of Digital Systems I. Diagnostic Modeling. Tallinn, Tallinn Technical University, 2005, 148 p. (in Estonian).
  3. Fehler in Automaten. (by D. Bochmann and R. Ubar), VEB  Verlag  Technik, Berlin, 1989, 216 p.
  4. Design of Digital Systems for Testability. (R. Ubar),  Tallinn  Technical University, 1988,  68 p. (in Russian).
  5. Operational Automata in Digital Computers (R.Ubar), Tallinn Technical University, 1987, 96 p. (in Estonian).
  6. P.Kitsnik, T.Lohuaru, R.Ubar. Test Design System for Digital Automata. Tallinn Techn. University, 1984, 58p. (in Russian)
  7. Design of Automatic Test Equipments. (A. Seleznev, B. Dobriza, R. Ubar), Mashinostrojenie, Moscow, USSR, 1983, 224 p., (in Russian).
  8. Testing of Digital Circuits. I. (R. Ubar),  Tallinn  Techn.  University, 1980, 114 p.  (in Russian).
  9. Testing of Digital Circuits. II. (R. Ubar), Tallinn  Techn.  University, 1981, 112 p.  (in Russian).
  10. Functional blocks in Digital Computers (R.Ubar), Tallinn Technical University, 1978, 103p. (in Estonian)

Papers:

2008

  1. R.Ubar, S.Devadze, J.Raik, A.Jutman. Fast Fault Simulation in Digital Circuits with Scan Path. 13th Asia and South Pacific Design Automation Conference – ASP-DAC 2008, Seoul, Korea, Jan. 21-24, 2008, (to appear).
  2. R.Ubar, S.Devadze, M.Jenihhin, J.Raik, G.Jervan, P.Ellervee. Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. 4th IEEE International Symposium on Electronic Design, Test & Applications – DELTA 2008, Hong Kong, January 23-25, 2008 (to appear).

2007

  1. J.Raik, R.Ubar, T.Viilukas, M.Jenihhin. Mixed Hierarchical-Functional Fault Models for Targeting Sequential Cores. Journal of Systems Architecture, 2007 [to appear]
  2. P.Ellervee, J.Raik, R.Ubar, K.Tammemäe. FPGA-Based Fault Emulation of Synchronous Sequential Circuits. IEE Proceedings on Computers & Digital Techniques. Vol.1, Issue 2, pp.70-76, March 2007.
  3. R.Ubar, A.Jutman, M.Kruus, E.Orasson, S.Devadze, H.-D.Wuttke. Learning Digital Test and Diagnostics via Internet. International Journal of Emerging Technologies in Learning. International Journal of Online Engineering, Vol.3, No.1, pp.1-9, 2007.
  4. R.Ubar, M.Kruus, T.Rang. Electronics Design and Test. Public Service Review: European Union, Issue 13, 2007, p.52-53.
  5. R.Ubar, S.Kostin, J.Raik. Fault Diagnosis in the BIST Environment Based on Bisection of Detected Faults. 8th IEEE Latin-American Test Workshop - LATW2007, Cuzco, Peru, March 11-14, 2007, pp.1-6.
  6. M.Jenihhin, J.Raik, R.Ubar, W.A.Pleskacz, M.Rakowski. Layout to Logic Defect Analysis for Hierarchical Test Generation. The 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems - DDECS 2007. Krakow, Poland, April 11-13, 2007, pp.35-40.
  7. J.Raik, V.Govind, R.Ubar. An External Diagnosis method for Network-on-a-Chip. IEEE/ACM Design Automation and Test in Europe Workshop on Diagnostic Services in Networks-on-Chips. April 16-20, Nice, France.   
  8. J.Raik, R.Ubar, V.Govind. Test Configurations for Diagnosing Faulty Links in NoC Switches. 12th IEEE European Test Symposium – ETS 2007, Freiburg, Germany, May 20-24, 2007, pp.29-34.
  9. R.Ubar, S.Devadze, J.Raik, A.Jutman. Ultra Fast Parallel Fault Analysis on Structural BDDs. 12th IEEE European Test Symposium – ETS 2007, Freiburg, Germany, May 20-24, 2007, pp.131-136.
  10. R.Ubar, T.Evartson, H.Lensen, M.Aarna. Hierarchical Fault Diagnosis in Embedded Digital Systems with Multi-Level Decision Diagrams. Proceedings 5th International Conference on Industrial Automation. ISBN 978-2-9802946-4-8. Universite de Quebec, Montreal, Canada. June 11-13, 2007, 4 p.
  11. R.Ubar, J.Raik, H.Kruus, H.Lensen, T.Evartson. Diagnostic Modelling of Digital Systems with Binary and High-Level Decision Diagrams. In “Progress in Industrial Mathematics at ECMI 2006”, Series: Mathematics in Industry, Subseries: The European Consortium for Mathematics in Industry , Vol. 12, Bonilla, L.L.; Moscoso, M.; Platero, G.; Vega, J.M. (Eds.), ISBN: 978-3-540-71991-5”, 2007 (available Dec.4, 2007).
  12. G.Jervan, H.Kruus, E.Orasson, R.Ubar. Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. IEEE 2nd International Symposium on Industrial Embedded Systems - SIES'2007. Lisbon, Portugal, 4-6 July 2007, pp.71-77.
  13. R.Ubar, A.Jutman, S.Devadze, H.-D. Wuttke. Bringing Research Issues into Lab Scenarios on the Example of SOC Testing. Proc. of International Conference on Engineering Education - ICEE 2007, Coimbra, Portugal, Sept. 3-7, 2007, pp.170-171. Full text on CD: ISBN:978-972-8055-14-1 (6 p.).
  14. G.Jervan, H.Kruus, E.Orasson, R.Ubar. Hybrid BIST Optimization Using Reseeding and Test Set Compaction. Proc. of 10th IEEE EUROMICRO Conference on Digital System Design - DSD 2007, Lübeck, Germany, August 27 - 31, 2007, pp.596-603.
  15. J.Raik, R.Ubar, A.Krivenko, M.Kruus. Hierarchical Identification of Untestable Faults in Sequential Circuits. Proc. of 10th IEEE EUROMICRO Conference on Digital System Design - DSD 2007, Lübeck, Germany, August 27 - 31, 2007, pp.668-671.
  16. R.Ubar, S.Kostin, J.Raik, T.Evartson, H.Lensen. Fault Diagnosis in Integrated Circuits with BIST. Proc. of 10th IEEE EUROMICRO Conference on Digital System Design - DSD 2007, Lübeck, Germany, August 27 - 31, 2007, pp.604-610.
  17. R.Ubar, S.Kostin, J.Raik, M.Kruus. Experimental Comparison of Different Diagnosis Algorithms in the BIST Environment. IASTED Conference on Applied Simulation and Modelling - ASM 2007, ACTA Press, August 29-31, 2007, Palma de Mallorca, Spain, pp.271-276.
  18. G.Guglielmo, F.Fummi, M.Jenihhin, G.Pravadelli, J.Raik, R.Ubar. On the Combined Use of HLDDs and EFSMs for Functional ATPG. EWDTS, Jerevan, 2007, pp.503-508.
  19. H.-D. Wuttke, R. Ubar, K. Henke, A. Jutman, “Assessment of Student’s Design Results in E-Learning-Scenarios”,  in Proc. of 8th Int. Conf. on Information Technology Based Higher Education and Training (ITHET’2007), Kumamoto, Japan, July 10-13, 2007, pp.1-6.
  20. R.Ubar, G.Jervan, J.Raik, M.Jenihhin, P.Ellervee. Dependability Evaluation in Fault-Tolerant Systems with High-Level Decision Diagrams. Proceedings of the 52. International Scientific Colloquium, Vol. II, Ilmenau, Sept. 10-13, 2007, pp.147-152.
  21. R.Ubar, S.Devadze, J.Raik, A.Jutman. Parallel Fault Backtracing for Calculation of Fault Coverage. International Conference on Microelectronics, Devices and Materials MIDEM, Workshop on electronic testing. Bled, Slovenia, September 12-14, 2007, pp.165-170.
  22. M.Jenihhin, J.Raik, A.Chepurov, R.Ubar. Assertion Checking with PSL and High-Level Decision Diagrams. Diggest of Papers IEEE 8th Workshop on RTL and High Level Testing - WRTLT'07. Beijing, P.R.China, Oct. 12-13, 2007, pp.105-110.
  23. A.Jutman, A.Tsertov, A.Tsepurov, I.Aleksejev, R.Ubar, H.-D.Wuttke, “BIST Analyzer: a Training Platform for SoC Testing” in Proc. of Frontiers in Education Conference (FIE’07), Milwaukee, Wisconsin, USA, October 10-13, 2007.

2006

  1. G.Jervan, Z.Peng, T.Shchenova, R.Ubar. A Hybrid BIST Energy Minimization Technique for SoC Testing. IEE Proceedings on Computers & Digital Techniques, July 2006, Vol. 153, Issue 4, pp.208-216.
  2. W.A.Pleskacz, T.Borejko, A.Walkanis, V.Stopjakova, A.Jutman, R.Ubar. DefSim: CMOS Defects on Chip for Research and Education. 7th IEEE Latin-American Test Workshop, March 26-29, 2006, Buenos Aires, Argentina, pp.74-79.
  3. S,Devadze, J.Raik, A.Jutman, R.Ubar. Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using Structurally Synthesized BDDs. 7th IEEE Latin-American Test Workshop, March 26-29, 2006, Buenos Aires, Argentina, pp.97-102.
  4. R.Ubar, A.Jutman, M.Kruus, H.-D.Wuttke. Applets for Learning Digital Design and Test. 1st Int. Conf. on Interactive Mobile and Computer Aided Learning - IMCL2006, Amman, Jordan, April 19-21, 2006, pp.1-6.
  5. T.Borejko, A.Jutman, W.Pleskacz, R.Ubar. DefSim: Measurement Environment for CMOS Defects. Proc. 25th International Conference on Microelectronics (MIEL’2006), Vol. 2, Belgrade, Serbia and Montenegro, 14-17 May 2006, pp.679-682.
  6. W.Pleskacz, T.Borejko, A.Walkanis, V.Stopjakova, A.Jutman, R.Ubar. CMOS Defects Analysis using DefSim Measurement Environment. Informal Digest of Papers of the 11th IEEE European Test Symposium, Southampton, UK, May 22-25, 2006, pp.241-246.
  7. R.Ubar, T.Evartson, M.Kruus, H.Lensen, J.Raik. Diagnostic Modelling of Digital Systems with Multi-Level Decision Diagrams. Proc. of the 17th IASTED International Conference on Modelling and Simulation. Montreal, May 24.-26, 2006, pp. 207-212.
  8. A.Jutman, A.Tsertov, R.Ubar. A Tool for Teaching Pseudo-Random TPG Principles. 17th  EAEEIE Conf. on Innovation in Education for Electrical and Information Engineering, Craiova, Romania, June 1-3, 2006, pp. 182-187.
  9. A. Jutman, W. A. Pleskacz, N. Boiko, R. Ubar. DefSim-Based Exercises for Studying Defects in CMOS Gates'. Proc. of 6th European Workshop on Microelectronics Education -EWME2006, Stockholm, Sweden, June 8-9, 2006.
  10. T.Bengtsson, A.Jutman, S.Kumar, Z.Peng, R.Ubar. Off-line Testing of Delay Faults in NoC Interconnects. Proceedings of the 9th IEEE EUROMICRO Conference on Digital Systems Design DSD2006, Katvat, Croatia, 2006, pp.677-680.
  11. J.Raik, R.Ubar. T.Viilukas. High-Level Decision Diagram based Fault Models for Targeting FSMs. Proceedings of the 9th IEEE EUROMICRO Conference on Digital Systems Design DSD2006, Katvat, Croatia, 2006, pp.353-358.
  12. T.Bengtsson, A.Jutman, S.Kumar, R.Ubar, Z.Peng. Analysis of a Test Method for Delay Faults in NoC Interconnects. Proc. of the IEEE East-West Design and Test Workshop. Sochi, Russia, Sept. 15.-19, 2006, pp. 42-46.
  13. V.Govind, J.Raik, R.Ubar. A Generic Synthesizable NoC Switch with Scalable Testbench. Baltic Electronics Conference. Laulasmaa, Oct. 2006, pp.91-94.
  14. A.Jutman, A.Tsertov, R.Ubar. A Tool for Advanced learning of LFSR-based Testing Principles. Baltic Electronics Conference. Laulasmaa, Oct. 2006, pp.175-178.
  15. J.Aleksejev, A.Jutman, R.Ubar. LFSR Polynomial and Seed Selection Using Genetic Algorithm. Baltic Electronics Conference. Laulasmaa, Oct. 2006, pp.179-182.
  16. R.Ubar, G.Jervan, H.Kruus, E.Orasson, I.Aleksejev. Optimization of the Store-and-Generate Based Built-in Self-Test. Baltic Electronics Conference. Laulasmaa, Oct. 2006, pp.199-202.
  17. R.Ubar, M.Brik, A.Jutman, J.Raik, T.Bengtsson, S.Kumar. Functional Test Generation for Finite State Machines. Baltic Electronics Conference. Laulasmaa, Oct. 2006, pp.205-208.
  18. G.Jervan, R.Ubar, Z.Peng. Hybrid BIST Methodology for Testing Core-Based Systems. Proc. of the Estonian Academy of Sciences. Engineering, 12 (2/3), pp.300-322.
  19. P.Ellervee, J.Raik, K.Tammemäe, R.Ubar. Environment for FPGA Based Fault Emulation. Proc. of the Estonian Academy of Sciences. Engineering 12 (2/3), pp.323-335.
  20. G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. J. of Computer Science and Technology. Nov. 2006, Vol. 21, No. 6, pp. 907-912.
  21. M.Kruus, R.Ubar. Success Story of the Computer Engineering Department at the Tallinn University of Technology in EU Projects. The Parliament Magazine. No. 234, 13. Nov. 2006, pp.33.
  22. V.Govind, J.Raik, R.Ubar. An External Test Approach for Network-on-Chip Switches. IEEE Asian test Symposium. 2006, Fukuoka, Japan, pp.437-442.
  23. T.Bengtsson, S.Kumar, A.Jutman, R.Ubar. Off-line Testing of Crosstalk Induced Glitch Faults in NoC Interconnects. 24th IEEE Norchip Conference, Linköping, Nov. 20-21, 2006, pp.221-226.
  24. G.Jervan, T.Shchenova, R.Ubar (2006). Hybrid BIST Scheduling for NoC-Based SoCs. 24th IEEE Norchip Conference, Linköping, Nov. 20-21, 2006, pp.141-144.
  25. R.Ubar, J.Raik, A.Jutman, P.Ellervee. Digital Electronics Design and Test at Computer Engineering Department of Tallinn University of Technology. The House Magazine. The Parlamentary Weekly, No 1198, Vol.32, Dec.11, 2006, pp.42.

2005

  1. J.Raik, R.Ubar, S.Devadze, A.Jutman. Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. Lecture Notes in Computer Science, Vol. 3463, Springer Verlag, Berlin, Heidelberg, New York 2005, pp. 332-344.
  2. J.Raik, T.Nõmmeots, R.Ubar. A New Testability Calculation Method to Guide RTL Test Generation. Journal of Electronic Testing: Theory and Applications – JETTA. Springer Science + Business Media, Inc. 21, pp.73-84, 2005.
  3. G.Jervan, R.Ubar, Z.Peng, P.Eles. Test Generation: A Hierarchical Approach. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 63-77.
  4. G.Jervan, R.Ubar, Z.Peng, P.Eles. An Approach to System Level DFT. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 91-118.
  5. A.Matrosova, A.Pleshkov, R.Ubar. Test Generation for Combinational Circuits by Orthogonal Disjunctive Normal Forms and SSBDDs. Avtomatika i Telemekhanika, No. 2, 2005, pp. 158–174 (in Russian).
  6. A.Matrosova, A.Pleshkov, R.Ubar. Construction of the Tests of Combinational Circuit Failures by Analyzing the Orthogonal Disjunctive Normal Forms Represented by the Alternative Graphs. J. of Automation and Remote Control. Publisher: Springer Science & Business Media B.V., 66 (2), 2005, pp. 313-327.
  7. J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz, W.Pleskacz. Deterministic Defect-Oriented Test Generation for Digital Circuits. 6th IEEE Latin-American Test Workshop – LATW2005, March 30 – April 2, 2005, Salvador, Bahia, Brazil, pp.325-330.
  8. G.Jervan, Z.Peng, R.Ubar, O.Korelina. An Improved Estimation Technique for Hybrid BIST Test Set Generation. Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron, April 13-16, 2005, pp.182-185.
  9. A.Jutman, R.Ubar, J.Raik. Generic Interconnect BIST for Network-on-Chip. Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron, April 13-16, 2005, pp.224-227.
  10. O.Novak, E.Gramatova, R.Ubar. IST Project REASON – Handbook of Testing Electronic Systems. Proc. of 5th European Dependable Computing Conf. – EDCC-5, Budapest, April 20-22, 2005, pp.15-18.
  11. R.Ubar, T.Shchenova, G.Jervan, Z.Peng. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. Proc. of 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.2-7.
  12. J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz, W.Pleskacz. DOT: New Deterministic Defect-Oriented ATPG Tool. Proc. of 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.96-101.
  13. Y.A.Skobtsov, D.E.Ivanov, V.Y.Skobtsov, R.Ubar, J.Raik. Evolutionary Approach to Test Generation for Functional BIST. Informal Digest of Papers of the 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.151-155.
  14. A.Jutman, R.Ubar, V.Rosin. A Software System fror IEEE 1149.1 Boundary Scan Design, Simulation and Demonstration. IEEE European Board Test Workshop, Tallinn, May 25-26, 2005, http://www.dft.co.uk/EBTW2005/PAPERS/.
  15. A.Jutman, V.Rosin, A.Sudnitson, R.Ubar, H.-D.Wuttke A System for Teaching Basic and Advanced Topics of IEEE 1149.1 Boundary Scan Standard. EAEEIE, June 2005. Best Paper Award.
  16. T.Bengtsson, A.Jutman, S.Kumar, R.Ubar. Delay Testing of Asynchronous NOC Interconnects. 12th International Conference Mixed Design of Integrated Circuits and Systems Kraków, 22-25 June 2005, pp.419-424.
  17. M.Balas, M.Fisherova, E.Gramatova, A.Jutman, Z.Kotasek, O.Novak, T.Pikula, J.Raik, J.Strnadel, R.Ubar, J.Zahradka. Testing Tools for Training and Education. 12th International Conference Mixed Design of Integrated Circuits and Systems Kraków, 22-25 June 2005, pp.671-676.
  18. R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Teaching Advanced Test Issues in Digital Electronics. 6th IEEE International Conference on Information Technology Based Higher Education and Training. July 7-9, 2005, Santo Domingo,  pp. S2B-5 – S2B-10.
  19. A.Jutman, R.Ubar, J.Raik. New Built-In Self-Test Scheme for SoC Interconnect. 9th World Multi-Conference on Systemics, Cybernetics and Informatics. July 10-13, 2005, Orlando, Florida, USA, vol.4, pp.19-24.
  20. J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Improved Fault Emulation for Synchronous Sequential Circuits. 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.72-78.
  21. A.Jutman, J.Raik, R.Ubar, V.Vislogubov. An Educational Environment for Digital Testing: Hardware, Tools, and Web-based Runtime Platform. 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.412-419.
  22. J.Sudbrock, J.Raik, R.Ubar, W.Kuzmicz, W.Pleskacz. Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.79-82.
  23. R.Ubar, H.-D.Wuttke. Research and Training Environment for Digital Design and Test. Proc. of the  8th  IASTED Int. Conf. on Computers and Advanced Technology in Education. Oranjestadt, Aruba, August 29-31, 2005, pp.232-237.
  24. R.Ubar. Decision Diagrams and Digital Test. 41th International Conference on Microelectronics, Devices and Materials – MIDEM 2005, Ribno at Bled, Slovenia, Sept. 14.-16, 2005, pp.15-26. Invited plenary paper.
  25. M.Brik, E.Fomina, R.Ubar. A Proposal for Optimisation of Low-Powered FSM Testing. 3rd East-West Design & Test Workshop EWDTW-2005, Odessa, Sept. 15-18, 2005, pp.15-20.
  26. E.Gramatova, M.Fisherova, R.Ubar, W.Pleskacz. Defects, Faults and Fault Models. In “Handbook of Electronic Testing”. CTU Printhouse, Prague, 2005, pp. 26-98.
  27. R.Ubar, E.Gramatova, M.Fisherova. Test Generation Techniques and Algorithms. In “Handbook of Electronic Testing”. CTU Printhouse, Prague, 2005, pp. 100-174.
  28. T.Bengtsson, A.Jutman, R.Ubar, S.Kumar. A method for crosstalk fault detection in on-chip Buses. IEEE NORCHIP Conference, Oulu, Finland, Nov. 21-22, 2005, pp.285-288.
  29. R.Ubar, P.Prinetto, J.Raik. 10th IEEE European Test Symposion. IEEE Journal of Design & Test of Computers, Sept.-Oct, 2005, pp.480-481.
  30. R.Ubar, M.Aarna, H.Kruus, J.Raik. High Quality Test Generation for Digital Systems. Romanian Journal of Information Science and Technology, Vol.8, No 1, 2005, pp.73-84.
  31. R.Ubar. Decision Diagrams and Digital Test. Informacije MIDEM-Journal of Microelectronics Electronic Components and Materials, 35(4), 2005, pp.187 - 195.

2004

  1. R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. Hybrid BIST Optimization for Core-Based Systems with Test Pattern Broadcasting. 2nd IEEE Int. Workshop on Electronic Design, Test and Applications – DELTA’04, Perth, Australia, 28-30 January 2004, pp.3-8.
  2. R.Ubar, H.-D.Wuttke. Research and Training Scenarios for Design and Test of SOC. Proc. of the World Congress on Engineering and technology Education. March 14-17, 2004, Guaruja/Santos, Brasil, pp.320-324.
  3. R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture. 5th IEEE Latin-American Test Workshop – LATW 2004. Digest of Papers, Cartagena, Colombia, March 8-10, 2004, pp.98-103.
  4. A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. 5th European Workshop on Microelectronics Education – EWME 2004, Lausanne, April 15-16, 2004, pp. 173-176
  5. J.Raik, R.Ubar. Enhancing Hierarchical ATPG with a Functional Fault Model for Multiplexers. 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems – DDECS 2004. Stara Lesna, Slovakia, April 18-21, 2004, pp. 219-222.
  6. R.Ubar, M. Kruus, E.Rüstern. EE: Eesti (Estonia). In “Towards the Harmonisation of Electrical and Information Engineering Education in Europe”. THEIERE, Brussels. CD - ISBN 972-97738-3-1, August, 2003, pp. 68-75.
  7. J.Raik, R.Ubar. Targeting Conditional Operations in Sequential Test Pattern Generation. IEEE European Test Symposium, Ajaccio, Corsica, France, May 23-26, 2004, pp. 17-18.
  8. A.Jutman, E.Gramatova, T.Pikula, R.Ubar. E-Learning Tools for Teaching Self-Test of Digital Electronics. 15 EAEEIE International Conf. on Innovation in Education for Electrical and Information Engineering, Sofia, Bulgaria, May 27-29, 2004, pp. 267-272.
  9. A.Jutman, ASudnitson, R.Ubar, H.-D.Wuttke. E-Learning Environment in the Area of  Digital Microelectronics. Proc. of the 5th Int. Conf. on Information Technology Based Higher Education and Training - ITHET 2004, Istambul, Turkey, 31 May – 2 June 2004, pp.278-283.
  10. R.Ubar, N.Mazurova, J.Smahtina, E.Orasson, J.Raik. HyFBIST: Hybrid Functional Built-In Self-Test in Microprogrammed Data-Paths of Digital Systems. Int. Conference MIXDES, Szczecin, June 24-26, 2004, pp.497-502.
  11. J.Raik, E.Orasson, R.Ubar. Sequential Circuits BIST with Status BIT Control. Int. Conference MIXDES, Szczecin, June 24-26, 2004, pp.507-510.
  12. R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architectures. System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004.
  13. R.Ubar, T.Vassiljeva, J.Raik, A.Jutman, M.Tombak, A.Peder. Optimization of Structurally Synthesized BDDs. The 4th IASTED International Conference on Modelling, Simulation and Optimization, Kauai, Hawaii, USA, August 17-19, 2004, pp.234-240.
  14. E. Ivask, J. Raik, R. Ubar, A. Schneider. WEB-Based Environment: Remote Use of Digital Electronics Test Tools. In “Virtual Enterprises and Collaborative Networks”, Kluwer Academic Publishers, 2004, pp. 435-442.
  15. R.Ubar. Diagnostic Modelling of Digital Systems with Decision Diagrams. Proceedings of Tomsk State University, No 9 (I), August 2004,  pp.174-179.
  16. J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Fast Fault Emulation for Synchronous Sequential Circuits. 2nd East-West Design & Test Workshop EWDTW-2004, Alushta 23-26, 2004, pp.35-40.
  17. M.Brik, J.Raik, R.Ubar, E.Ivask. GA-based Test Generation for Sequential Circuits. 2nd East-West Design & Test Workshop EWDTW-2004, Alushta 23-26, 2004, pp.30-34.
  18. R.Ubar, M.Aarna, M.Brik, J.Raik. High_Level Fault Modeling in Digital Systems. 49. Int. Conf.  Shaker Verlag, Aachen, 2004, pp.486-491.
  19. E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, H-D.Wuttke. Research Environment for Teaching Digital Test. 49. Int. Conf.  IWK, Ilmenau, Germany, September 27-30, 2004, pp.468-473.
  20. A.Jutman, A.Peder, J.Raik, M.Tombak, R.Ubar. Structurally Synthesized Binary Decision Diagrams. 6th International Workshop on Boolean Problems, Freiberg, Germany, Sept. 2004, pp.271-278.
  21. N.Mazurova, J.Smahtina, R.Ubar. Hybrid Functional BIST for Digital Systems. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.205-208.
  22. J.Raik, A.Krivenko, R.Ubar. Comparative Analysis of Sequential Circuit Test Generation Approaches. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.225-228.
  23. Y.A.Skobtsov, D.E.Ivanov, V.Y.Skobtsov, R.Ubar. Evolutionary approach to the functional test generation for digital circuits. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.229-232.
  24. M.Brik, E.Ivask, J.Raik, R.Ubar. On Using Genetic Algorithm for Test Generation. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.233-236.
  25. V.Vislogubov, A.Jutman, H.Kruus, E.Orasson, J.Raik, R.Ubar. Diagnostic Software with WEB Interface for Teaching Purposes. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.255-258.
  26. R.Ubar, M.Aarna, H.Kruus, J.Raik. How to Generate High Quality Tests for Digital Systems. IEEE International Semiconductor Conference, CAS’2004, Sinaia, Romania, Oct. 4-6, 2004, pp.459-462.
  27. Jutman, A. Sudnitson, R. Ubar, and H.-D. Wuttke, "Asynchronous E-Leaning Resources for Hardware Design Issues", in Proc. International Conference on Computer Systems and Technologies  (CompSysTech'2004), Sofia, Bulgaria, 2004, v. IV, pp. 11.1-11.6. (ISBN: 954-9641-38-4).
  28. R.Ubar, H-D.Wuttke. Research and Training Environment for Digital Design and Test.  34th ASEE/IEEE Frontiers in Education Conference, October 20-23, 2004, Savannah, GA, pp.S3F-18 to S3F-24. IEEE Catalog Number: 04CH37579. ISBN: 0-7803-8552-7. Library of Congress: 79-640910. ISSN: 0190-5848.
  29. P.Ellervee, J.Raik, V.Tihhomirov, R.Ubar. FPGA Based Fault Emulation of Synchronous Sequential Circuits. Proc. of the 22nd IEEE Norchip Conference, Oslo, November 8-9, 2004, pp.59-62.
  30. G.Jervan, Z.Peng, R.Ubar, O.Korelina. An Improved Estimation Methodology for Hybrid BIST Cost Calculation. Proc. of the 22nd IEEE Norchip Conference, Oslo, November 8-9, 2004, pp.297-300.
  31. J.Raik, V.Govind, R.Ubar. RT-Level Test Point Insertion for Sequential Circuits. Proc. of  the IEEE 1st International Workshop on Testability Assessment – IWoTA-2004, Rennes, Nov.2, 2004, pp.34-40. IEEE Catalog Number 04EX983, ISBN 0-7803-8851-8.
  32. V.Hahanov, R.Ubar. 2nd IEEE EastWest Design & Test Workshop. IEEE Journal of Design & Test of Computers, Nov.-Dec 2004, pp.594.
  33. A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. In “Microelectronics Education” Kluwer Academic Publishers, 2004, pp.253-258.

2003

  1. R.Ubar. Design Error Diagnosis with Resynthesis in Combinational Circuits. Journal of Electronic Testing: Theory and Applications 19, 73-82, 2003. Kluwer Academic Publishers.
  2. R.Ubar, J.Raik. Testing Strategies for Networks on Chip. In “Networks on Chip” by A.Jantsch, H.Tenhunen. Kluwer Academic Publishers, 2003, pp. 131-152.
  3. J.Raik, T.Nõmmeots, R.Ubar. New Method of Testability Calculation to Guide RT-Level Test Generation. Proc. of 4th IEEE Latin-American Test Workshop – LATW2003, Natal, Brazil, February 16-19, 2003, pp.46-51.
  4. R.Ubar, E.Orasson. E-Learning tool and Exercises for Teaching Digital Test. Proc.of 2nd IEEE Conf. on Signals, Systems, Decision and Information Technology. Sousse, Tunisia, March 26-28, 2003, CIT-6, pp.1-6.
  5. R.Ubar. Decision Diagrams and Digital Test. Proc. of the 6th International Workshop on Electronics, Control, Measurement and Signals, Liberec, Czechia, June 2-4, 2003, pp.266-273 (Invited plenary paper).
  6. A. Jutman, A. Sudnitson, R. Ubar. Web-Based Training System for Teaching Principles of Boundary Scan Technique. EAEEIE, Poland.
  7. R.Ubar, J.Raik, B.Klüver. Algorithms for hierarchical fault simulation in digital systems. Proc. of the 10th Int. Conf. MIXDES 2003, Lodz, June 26-28, 2003, pp.530-535.
  8. A.Jutman, A.Sudnitsõn, R.Ubar. Web-Based Applet for Teaching Boundary Scan standard IEEE 1149.1. Proc. of the 10th Int. Conf. MIXDES 2003, Lodz, June 26-28, 2003, pp.584-589 (Best Paper Award).
  9. R.Ubar. E-Learning Tools for the Field of Electronics Design and Test. Proc. of the 4th Int. Conf. On Information Technology Based Higher Education and Training. Marrakech, Morocco, July 7-9, 2003, pp.285-290.
  10. A.Jutman, A.Sudnitsõn, R.Ubar, D.Wuttke. Java Applets Support for an Asynchronous-Mode Learning of Digital Design and Test. Proc. of the 4th Int. Conf. On Information Technology Based Higher Education and Training. Marrakech, Morocco, July 7-9, 2003, pp.397-401.
  11. R.Ubar. Mapping Physical Defects to Logic Level for Defect Oriented Testing. Proc. Of International Symposium on Signals, Circuits and Systems – SCS 2003, Vol. 2, Iasi, Romania, July 10-11, 2003, pp.453-456.
  12. A.Schneider, K.-H.Diener, G.Elst, R.Ubar, E.Ivask, J.Raik. Integration of Digital Test Tools to the Internet-Based Environment MOSCITO. Proc. of 7th World Multiconference on Systemics, Cybernetics and Informatics – SCI 2003. Orlando, USA, July 27-30, 2003, pp.136-141.
  13. R.Ubar. Mapping Faults in Hierarchical testing of Digital Systems. Proc. of the Int. Conf. On Computer, Communication and Control technologies – CCCT’03. Orlando, USA, July 31 – August 2, 2003, pp.14-19. (Best Paper Award)
  14. V.Hahanov, R.Ubar, S.Hyduke. Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. Proc. of EUROMICRO Symposion on Digital System Design - DSD’2003. Belek-Antalaya, Turkey, September 3-5, 2003, pp. 370-377.
  15. V.Hahanov, R.Ubar. Design Technologies for System-on-Chip: Fault Simulation in Complex Digital Designs. Proc. of Avtomatizirovannyje Sistemy Upravlenija i Pribory Avtomatiki”,  No 122, 2003, pp.16-35 (in Russian).
  16. J.Raik, R.Ubar. DECIDER: A System for Hierarchical Test Pattern Generation. J. of Radioelectronics and Informatics, No3 (24), July – September, 2003, pp. 40-45.
  17. M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.D.Wuttke. Turbo Tester – Diagnostic Package for Research and Training. J. of Radioelectronics and Informatics, No3 (24), July – September, 2003, pp. 69-73.
  18. G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. 18th Int. Symposium on Defect and Fault Tolerance in VLSI Systems. Cambridge, MA, USA, November 3-5, 2003.
  19. G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003, Xi’an, China, November 17-19, 2003, pp. 318-323.
  20. R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting. 21st IEEE Conference NORCHIP’2003, Riga, Latvia, November 10-11, 2003, pp.112-116.
  21. J.Raik, R.Raidma, R.Ubar. Explorations in Low Area Overhead DfT Techniques for Sequential BIST. 21st IEEE Conference NORCHIP’2003, Riga, Latvia, November 10-11, 2003, pp.220-223.
  22. Jutman, A. Sudnitson, and R. Ubar, "Digital Design Learning System Based on Java Applets", in Proc. 4th Annual Conference of the LTSN Centre for Information and Computer Sciences, NUI Galway, Ireland, 2003, pp.183-187  (ISBN: 0-9541927-4-5).
  23. E.Gramatova, M.Hristov, W.Kuzmicz, V.Lantsov, M.Lobur, V.Nelayev, V.Stepanets, R.Ubar, H.-D.Wuttke. Results of International Cooperation for Development and Exchange of Web-Based Educational Materials. In “Distance Learning – Educational Environment of the XXI Century”, Minsk, 2003, pp. 17-23.
  24. V.Hahanov, R.Ubar. First East-West Design and Test Conference. IEEE Design & Test, Nov.-Dec 2003, pp.103.
  25. R.Ubar, E.Rüstern, M.Kruus. EE: Eesti (Estonia) in “Towards the Harmonization of Electrical and Information Engineering Education in Europe”, Lisboa-Nancy 2003, Ed. EAEEIE, 2003, pp.67-74.

2002

  1. R.Ubar, J.Raik, E.Ivask, M.Brik. Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. IEEE Workshop on Electronic Design, Test and Applications – DELTA’02, Christchurch, New Zealand, 29-31 January 2002, pp.86-91.
  2. R.Ubar. Testability Calculation for Digital Circuits with Decision Diagrams. 3rd IEEE Latin-American Test Workshop – LATW’2002, Montevideo, Uruguay, February 10-13, 2002, pp.137-143.
  3. T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation for Combinational Circuits with Real Defects Coverage. Pergamon Press. Journal of Microelectronics Reliability, Vol. 42, 2002, pp.1141-1149.
  4. A.Schneider, E.Ivask, P.Mikloš, J.Raik, K.H.Diener, R.Ubar, T.Cibáková, E.Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proc. of  Design Automation and Test in Europe – DATE’02. Paris, March  4-8, 2002, pp. 221-226.
  5. G.Jervan, H.Kruus, Z.Peng, R.Ubar. About Cost Optimization of Hybrid BIST in Digital Systems. 3rd Int. Symp. on Quality of Electronic Design, San Jose, California, March 18-20, 2002, pp.273-279.
  6. R.Ubar, J.Raik, E.Ivask, M.Brik. Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta Universitatis (Nis), Ser.: Elec. Energ. Vol.15, No.1, April 2002, pp.123-136.
  7. R.Ubar, E.Orasson, T.Evartson. Java Applet for Self-Learning of Digital Test Issues. 13th EAEEIE Conference, York, Great Britannia, April 8-10, 2002.
  8. R.Ubar, J.Raik, E.Ivask, M.Brik. Mixed-Level Defect Simulation in Data-Paths of Digital Systems. 23rd Int. Conf. on Microelectronics. Nis, Yugoslavia, May 12-15 2002, Vol.2, pp.617-620.
  9. A.Jutman, J.Raik, R.Ubar. On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model. 23rd Int. Conf. on Microelectronics. Nis, Yugoslavia, May 12-15 2002, Vol.2, pp.621-624.
  10. R.Ubar, A.Jutman, E.Orasson, J.Raik, T.Evartson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. In the book "Microelectronics Education", Marcombo Boixareu Ed., 2002, pp.317-320.
  11. J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Sequential Circuit Tests Using Branch-and-Bound and Search State Registration. 7th IEEE European Test Workshop, Corfu, May 26-29, 2002, pp.19-20.
  12. A.Jutman, J.Raik, R.Ubar. SSBDD Model: Advantageous Properties and Efficient Simulation Algorithms. 7th IEEE European Test Workshop, Corfu, May 26-29, 2002, pp.345-346.
  13. S.Devadze, A.Jutman, A.Sudnitsõn, R.Ubar. WEB-Based Training System for Teaching Basics of RT-Level Digital Design, Test and Design for Test. Proc. of the 9th Int. Conf. MIXDES 2002, Wroclaw, June 20-22, 2002, pp.699-704. 
  14. T.Nõmmeots, J.Raik, R.Ubar. Testability Analysis for Efficient Register-Transfer Level Test Generation. Proc. of the 9th Int. Conf. MIXDES 2002, Wroclaw, June 20-22, 2002, pp.555-558.
  15. A.Schneider, K.-H.Diener, E.Ivask, R.Ubar, E.Gramatova, T.Hollstein, W.Pleskacz, W.Kuzmicz, Z.Peng. Integrated Design and Test Generation Under Internet Based Environment MOSCITO. EUROMICRO Conference, September 3-6, 2002, pp. 187-194.
  16. R.Ubar, J.Raik, E.Ivask, M.Brik. Test Cover Calculation in Digital Systems with Word-Level Decision Diagrams. Proc. of the International Conference on Computer Dependability, Tomsk, Russia, September 10-13, 2002, pp.315-319. Invited paper.
  17. A. Jutman, J. Raik, R. Ubar. SSBDDs: Advantageous Model and Efficient Algorithms for Digital Circuit Modeling, Simulation & Test. 5th Int. Workshop on Boolean Problems. Freiberg, Germany, September 19-20, pp.157-166.
  18. A.Schneider, K.-H.Diener, E.Ivask, R.Ubar, E.Gramatova, M.Fisherova, W.Pleskacz, W.Kuzmicz. Defect-Oriented Test Generation and Fault Simulation in the Environment of MOSCITO. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.303-306.
  19. A.Schneider, K.-H.Diener, J.Raik, R.Ubar, G.Jervan, Z.Peng, T.Hollstein, M.Glesner. High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory. Proc. BEC-2002, Tallinn, October 6-9, 2002, pp.287-290.
  20. S.Devadze, A.Jutman, A.Sudnitsõn, R.Ubar, H.-D.Wuttke. Java Technology Based Training System for Teaching Digital Design and Test. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.283-286.
  21. J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Independent Test Sequences. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.315-318.
  22. R.Ubar, J.Raik, T.Nõmmeots. Testability Guided Hierarchical Test Generation with Decision Diagrams. 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.265-271.
  23. S.Devadze, A.Jutman, A.Sudnitson, R.Ubar, H.-D.Wuttke. Teaching Digital RT-Level Self-Test Using a Java Applet. 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.322-328.

2001

  1. R.Ubar. Design Error Diagnosis in Scan-Path Designs. 2nd Latin-American Test Workshop. Cancun, Mexico, February 11-14, 2001, pp. 162-168.
  2. A.Jutman, R.Ubar, Z.Peng. Algorithms for Speeding-Up Timing Simulation of Digital Circuits. DATE, Munich, March 13-16, 2001.
  3. R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. 2nd Int. Symp. on Quality of Electronic Design, San Jose, California, March 26-28, 2001.
  4. E.Ivask, R.Ubar, J.Raik, A.Schneider. Internet Based Test Generation and Fault Simulation. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.57-60.
  5. T.Cibaková, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Library Builder for Functional Test Generation. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.163-168.
  6. J.Raik, A.Jutman, R.Ubar. Fast and Efficient Static Compaction of Test Sequences Based on Greedy Algorithms. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.117-122.
  7. A.Schneider, E.Ivask, J.Raik, P.Miklos, K.H. Diener, R.Ubar, W.Kuzmicz, W. Pleskacz, E. Gramatova. VILAB Test Generation Tools Running Under the MOSCITO System. VILAB User Forum Györ, Hungary, April 18-20, 2001, 12 p.
  8. J.Mermet, A.Morawiec, R.Ubar. Methods for improving the performance of simulation. TIMA Laboratory, Annual Report 2000, Grenoble, May 2001, pp.90-94.
  9. J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Test Sequences Using Implications and greedy Search. Digest of European Test Workshop, Stockholm, May 29 – June 1, 20001, pp. 207-210.
  10. A.Jutman, R.Ubar. Laboratory Training for Teaching Design and Test of Digital Circuits. MIXDES’01, Zakopane, Poland, June 21-23, 2001, pp. 521-524.
  11. T.Cibakova, M.Fischerova, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Test Generation Using Probabilistic Estimation. MIXDES’01, Zakopane, Poland, June 21-23, 2001, pp.131-136.
  12. R. Ubar, J. Raik, E. Ivask, M. Brik. Hierarchical Fault Simulation in Digital Systems. Proceedings of  Int. Symp. on Signals, Circuits and Systems SCS’2001, Iasi, Romania, July 10-11, 2001, pp.181-184.
  13. T.Hollstein, Z.Peng, R.Ubar, M.Glesner. Challenges for Future System-on-Chip Design. Proceedings of European Conference on Circuit Theory and Design. Espoo, Finland, August 28-31, 2001,pp.173-176.
  14. R. Ubar, G.Jervan, Z.Peng, E.Orasson, R.Raidma. Fast Test Cost Calculation for Hybrid BIST in Digital Systems. Proc. of EUROMICRO Symposium on Digital Systems Design, Warsaw, September 4-6, 2001, pp.318-325.
  15. R.Ubar. Multi-Level Test Generation for Digital Systems at System, Circuit and Defect Levels. Proc. of 7th International Scientific Conference “Theory and Technique of Information Transmission, Reception and Processing”. Tuapse, October 1-4, 2001, pp.286-288.
  16. R.Ubar, H.-D.Wuttke. The DILDIS-Project – Using Applets for More Demonstrative Lectures in Digital Systems Design and Test. Proceedings of the 31st ASEE/IEEE Frontiers in Education Conference, FIE’2001, Oct. 10-13, 2001, Reno, NV, USA, pp.SIE-2-7.
  17. R.Ubar, H.-D.Wuttke. The DILDIS-Project – Using Applets for More Demonstrative Lectures in Digital Systems Design and Test. 31st ASEE/IEEE Frontiers in Education Conference. Abstracts, Oct. 10-13, 2001, Reno, NV, USA, pp.83.
  18. M.Aarna, J.Raik, R.Ubar. Parallel Fault Simulation in Digital Circuits. Proc. of 42th International Scientific Conference of Riga Technical University. Riga, October 11-13, 2001, pp.91-94.
  19. M.Blyzniuk, I.Kazymyra, W.Kuzmicz, W.A.Pleskacz, J.Raik, R.Ubar. Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvements. Journal of Microelectronics Reliability. Pergamon Press. Vol  41/12, Dec. 2001, pp 2023-2040.
  20. W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Module Level Defect Simulation in Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.253-268.
  21. A. Jutman, R. Ubar. Application of Structurally Synthesized Binary Decision Diagrams for Timing Simulation of Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.269-288.
  22. H.Kruus, R.Ubar, G.Jervan, Z.Peng. Using Tabu Search Method for Optimizing the Cost of Hybrid BIST. XVI Conference on Design of Circuits and Integrated Systems, Porto, Portugal, Nov. 20-23, 2001, pp.445-450.
  23. R.Ubar, J.Heinlaid, L.Raun. Improved Testability Calculation for Digital Circuits. 19th IEEE Conference NORCHIP’2001, Stockholm, Sweden, pp.264-270.

2000

  1. A.Jutman, R.Ubar. Design Error Diagnosis in Digital Circuits with Stuck-at Fault Model. Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.
  2. J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000.
  3. R.Ubar, A.Jutman. Design Error Localization in Digital Circuits by Stuck-at Fault Test Patterns. IEEE 22nd Int. Conference on Microelectronics, Nis, Yugoslavia, May 14-17 2000, pp.723-726.
  4. R.Ubar, J.Raik. Efficient Hierarchical Approach to Test Generation for Digital Systems. 1st Int. Symp. on Quality of Electronic Design, San Jose, California, March 20-22, 2000, pp. 189-195.
  5. R.Ubar, A.Morawiec, J.Raik. Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. IEEE Proc. of  Design Automation and Test in Europe. Paris, March  27-30, 2000, pp. 743.
  6. R.Ubar, A.Morawiec, J.Raik. Vector Decision Diagrams for Simulation of Digital Systems. DDECS’2000, Smolenice, April 5-7, 2000, pp. 44-51.
  7. R.Ubar, H.-D.Wuttke. Action Based Learning System for Teaching Digital Electronics and Test. Proc. of 3rd European Workshop on Microelectronics Education, Aix-en-Provence (France), May 18-19, 2000, pp.65-66.
  8. E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. IEEE European Test Workshop, Cascais, Portugal, Mai 23-26, 2000, pp. 319-320.
  9. M.Blyzniuk, FT.Cibakova, E.Gramatova,W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect-Oriented Fault Simulation for Digital Circuits. IEEE European Test Workshop, Cascais, Portugal, Mai 23-26, 2000, pp.151-156.
  10. R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams. Proc. of the IEEE ISCAS’2000 Conference, Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.
  11. M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Defect Oriented Fault Coverage of 100% Stuck-at Fault Test Sets. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.511-516.
  12. R.Ubar, M.Brik. Hierarchical Concurrent Test Generation for Synchronous Sequential Circuits. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.533-538.
  13. R.Ubar, A.Morawiec, J.Raik. High-Level Decision Diagrams for Simulation Performance. Proc. of the World Multiconference on Systemics, Cybernetics and Informatics, SCI- 2000. Orlando, Florida, USA, July 23-26, 2000. Vol. IX Industrial Systems, pp.62-67.
  14. M.Blyzniuk, FT.Cibakova, E.Gramatova,W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect-Oriented ault Simulation for Digital Circuits. IEEE Proceedings ETW 2000, Cascais, Portugal, Mai 23-26, 2000, pp.69-74.
  15. R.Ubar, E.Orasson, H.-D.Wuttke. Interactive Teaching Software “Introduction To Digital Test”. 45th International Conference, Ilmenau (Germany), October 4-6, 2000, pp.949-954.
  16. R.Ubar. Hierarchical Approach to Test Generation for Digital Systems at System, Circuit and Defect levels. 45th International Conference, Ilmenau (Germany), October 4-6, 2000, pp.711-716.
  17. K.-H.Diener, G.Elst, E.Gramatova, W.Kuzmicz, Z.Peng, R.Ubar. Virtual Laboratory for Research in Dependable Miroelectronics. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.217-220.
  18. R.Ubar, A.Jutman. BEC: Increasing the Speed of  Delay Simulation in Digital Circuits. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.31-34.
  19. R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Combining Learning, Training and Research in Laboratory Course for Design and Test. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, 221-224.
  20. A.Morawiec, J.Raik, R.Ubar. Simulation of Digital Systems with High-Level Decision Diagrams. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.35-38.
  21. M.Brik, J.Raik, R.Ubar. Hierarchical Fault Simulation for Finite State Machines. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.145-148.
  22. E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generator for Sequential Circuits Using Genetic Algorithms. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.129-132.
  23. G.Jervan, Z.Peng, R.Ubar. Test Cost Minimization for Hybrid BIST. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems. Tokio, October 25-28, 2000, pp.283-291.
  24. R.Ubar, A.Jutman, Z.Peng. Improving the Efficiency of Timing Simulation in Digital Circuits by Using Structurally Synthesized BDDs. IEEE Norchip conference, Turku, November 7-8, 2000, pp.254-261.
  25. R.Ubar. Removing Design Errors from Digital Circuits. Proc. of the 4th International Conference on New Information Technologies. Minsk, December 5-7, 2000, Volume 1, pp.118-125.
  26. R.Ubar, H.-D.Wuttke. Action Based Learning System for Teaching Digital Electronics and Test. In “Microelectronics Education”, Kluwer Academic Publishers, Dordrecht/ Boston/London, 2000, pp. 107-110.

1999

  1. T-S.Lande, R.Ubar. Guest Editorial. Analog Integrated Circuits and Signal Processing. Kluwer Publishers, Vol.18, No 1., January 1999, pp. 5-6.
  2. R.Leveugle, R.Ubar. Modeling VHDL Clock-Driven Multi-Processes by Decision Diagrams.  J. of Electron Technology, Vol. 32, (1999) No.3, pp.282-287.
  3. R.Ubar, D.Borrione. Single Gate Design Error Diagnosis in Combinational Circuits. Proceedings of the Estonian Acad. of Sci. Engng, 1999, Vol. 5 , No 1, pp.3-21.
  4. J.Raik, R.Ubar. Sequential Circuit Test Generation Using Decision Diagram Models. IEEE Proc. of  Design Automation and Test in Europe. Munich, March  9-12, 1999, pp. 736-740.
  5. R.Ubar, A.Moraviec, J.Raik. Cycle-based Simulation with Decision Diagrams. IEEE Proc. of  Design Automation and Test in Europe. Munich, March  9-12, 1999, pp.454-458.
  6. G.Elst, K-H.Diener, E.Ivask, J.Raik, R.Ubar. FPGA Design Flow with Automated Test Generation. Proc. of German 11th Workshop on Test Technology and Reliability of Circuits and Systems. Potsdam, 1999, pp. 120-123.
  7. R.Ubar, J.Raik. Hierarchical Test Generation for Complex Digital Systems with Control and Data Processing Parts. In “Test, Assembly and Packaging”, SEMICON Technical Symposium,  Singapur May 3-6, 1999, pp.43-52.
  8. R.Ubar, J.Raik. Hierarchical Test Generation. SEMI Show slides. In “Test, Assembly and Packaging”, SEMICON Technical Symposium,  Singapur May 3-6, 1999, pp. 53-64.
  9. J.Raik, R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation. Compendium of Papers. IEEE European Test Workshop, Constance, May 25-28, 1999, 5 p.
  10. R.Ubar, A.Jutman. Hierarchical Design Error Diagnosis in Combinational Circuits by Stuck-at Fault Test Patterns. Proc. of the 6th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow (Poland), June 17-19, 1999, pp. 437-442.
  11. A.Markus, J.Raik, R.Ubar. Fast and Efficient Static Compaction of Test Sequences Using Bipartite Graph Representations. Proc. of 2nd Electronic Circuits and Systems Conference. Bratislava, September 6-8, 1999, pp. 17-20.
  12. G.Jervan, P.Eles, Z.Peng, J.Raik, R.Ubar. High-Level Test Synthesis with Hierarchical Test Generation. IEEE 17th NORCHIP Conference, Oslo, Nov. 8-9, 1999, pp.291-296.
  13. M.Brik, R.Ubar. Two-Level Simulation-Based Test Generation for Finite State Machines.  IEEE 17th NORCHIP Conference, Oslo, Nov. 8-9, 1999, pp.211-216.
  14. R.Ubar, D.Borrione. Design Error Diagnosis in Digital Circuits without Error Model. 10th IFIP Int. Conf. on VLSI’99. Lisbon, Dec. 1-4, 1999, pp.281-292.
  15. J.Raik, R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation Proc. of IEEE European Test Workshop, Constance, May 25-28, 1999, pp.84-89.

1998

  1. Combining Functional and Structural Approaches in Test Generation for Digital Systems  (R.Ubar). Journal of Microelectronics and Reliability, Elsevier Science Ltd. Vol. 38:3, pp.317-329, 1998.
  2. Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams (R.Ubar). OPA (Overseas Publishers Assotiation) N.V. Gordon and Breach Publishers, Multiple Valued Logic, Vol.4  pp. 141-157, 1998.
  3. Dynamic Analysis of Digital Circuits with 5-valued Simulation (R. Ubar). In "Mixed Design of Integrated Circuits and Systems". Kluwer Academic Publishers, pp.187-192, 1998.
  4. Hierarchical Test Generation for Digital Systems (M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar). In "Mixed Design of Integrated Circuits and Systems". Kluwer Academic Publishers, pp.131-136, 1998.
  5. Turbo Tester: A CAD System for Teaching Digital Test (G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar). In "Microelectronics Education". Kluwer Academic Publishers, pp.287-290, 1998.
  6. Feasibility of Structurally Synthesized BDD Models for Test Generation (J.Raik, R.Ubar). Proc. of the IEEE European Test Workshop, Barcelona (Spain), May 27-29, 1998, pp.145-146.
  7. Hierarchical Test Generation with Multi-Level Decision Diagram Models (G.Jervan, A.Markus, J.Raik, R.Ubar). Proc. of the 7th IEEE North Atlantic Test Workshop,  West Greenwich RI, USA, May 28-29, 1998, pp.26-33.
  8. Mixed Bottom-Up/Top-Down Hierarchical Test Generation for Digital Systems (R.Ubar). Proc. of the 9th European Workshop on Dependable Computing, Gdansk (Poland), May 14-16, 1998, pp.37-40.
  9. Teaching Dependability Issues in System Engineering at the Technical University of Tallinn (R.Ubar). Preprints of Proceedings, 90th Anniversary Jubilee Seminar on Engineering Education. University of Wismar, Germany, May 6-8 1998, pp.1-5. Invited paper.
  10. Test Generation with Structurally Synthesized BDD Models (J.Raik, R.Ubar). Proceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 1998, pp.66-68.
  11. VHDL Based Test Generation System (G.Jervan, A.Markus, J.Raik, R.Ubar). Proceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 1998, pp.145-148.
  12. Mixed-Level Deterministic-Random Test Generation for Digital Systems (G.Jervan, A.Markus, J.Raik, R.Ubar). Proc. of the 5th International Conference on Mixed Design of Integrated Circuits and Systems. Lodz (Poland), June 18-20, 1998, pp. 335-340.
  13. Synthesis of Decision Diagrams from Clock-Driven Multi-Process VHDL Descriptions for Test Generation (R.Leveugle, R.Ubar). Proc. of the 5th International Conference on Mixed Design of Integrated Circuits and Systems. Lodz (Poland), June 18-20, 1998, pp. 353-358. Best Paper Award.
  14. Hierarchical Test Generation for Digital Systems Based on Combining Bottom-Up and Top-Down Approaches (J.Raik, R.Ubar). World Multiconference on Systemics, Cybernetics and Informatics. Orlando, Florida, July 12-16, 1998, Vol.1, pp. 374-381.
  15. Dynamic Analysis of Digital Circuits with Multi-Valued Simulation (R. Ubar). Microelectronics Journal, Elsevier Science Ltd., Vol. 29, No. 11, Nov. 1998, pp.821-826.
  16. Localization of Single-Gate Design Errors in Combinational Circuits by Diagnostic Information about Stuck-at Faults (R.Ubar, D.Borrione). Proc. of the 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems. Szczyrk, Poland, Sept. 2-4, 1998, pp.73-79.
  17. DECIDER: A Decision Diagram Based Hierarchical Test Generation System (G.Jervan, A.Markus, J.Raik, R.Ubar). Proc. of the 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems. Szczyrk, Poland, Sept. 2-4, 1998, pp.269-273.
  18. Generation of Tests for the Localization of Single-Gate Design Errors in Combinational Circuits Using the Stuck-at Fault Model (R.Ubar, D.Borrione). Proc. of the 11th IEEE Brasilian Symposium on Integrated Circuit Design. Rio de Janeiro, Brazil, Sept. 30 – Oct. 3, 1998, pp.51-54
  19. An Improved Test Generation Approach for Sequential Circuits using Decision Diagrams (M.Brik, R.Ubar). Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 155-158.
  20. A Decision Diagram Based Hierarchical Test Pattern Generator (G.Jervan, A.Markus, J.Raik, R.Ubar). Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 159-162.
  21. Comparison of Genetic and Random Techniques for Test Pattern Generation (E.Ivask, J.Raik, R.Ubar). Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 163-166.
  22. Test Set Minimization Using Bipartite Graphs  (A.Markus, J.Raik, R.Ubar). Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 175-178.
  23. Calculation of Testability Measures on Structurally Synthesized Binary Decision Diagrams (R.Ubar, J.Heinlaid, J.Raik, L.Raun). Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 179-182.
  24. Compaction of Decision Diagrams for Describing Multi-Process VHDL Descriptions (R.Leveugle, G.Saucier, R.Ubar). Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 195-198.
  25. Teaching Dependability Issues in System Engineering at the Technical University of Tallinn (R.Ubar). Global J. of Engineering Education, Vol.2, No 2, 1998 UICEE, Printed in Australia, pp. 215-218.

1997

  1. A New Approach to Build a Low-Level Malicious Fault List Starting from High-Level Description and Alternative Graphs (A. Benso, P.Prinetto, M.Rebaudengo, M.Sonza, R.Ubar). Proc. IEEE European Design & Test Conference, Paris, March 17-20, 1997.
  2. CAD Software for Digital Test and Diagnostics (G.Jervan, A.Markus, P.Paomets,J.Raik,  R.Ubar). Proc. of International Conference on Design and Diagnostics of Electronic Circuits and Systems. Beskydy Mountains, Czech Republic, May 12-16, 1997, pp.35-40.
  3. Multi-Valued Simulation with Binary Decision Diagrams (R.Ubar, J.Raik). Proc. IEEEEuropean Test Workshop, Cagliari (Italy), May 28-30, 1997, pp.28-29.
  4. Boolean Derivatives and Multi-Valued Simulation on Binary Decision Diagrams (R.Ubar). 4th International Workshop on Mixed Design of Integrated Circuits and Systems. Poznan, June 12-14, 1997, pp.115-120.
  5. A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs (M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar). 4th International Workshop on Mixed Design of Integrated Circuits and Systems. Poznan, June 12-14, 1997, pp.415-420.
  6. Representing Transparency Conditions in Test Generation for VLSI by Decision Diagrams (R.Ubar). The 1st Electronic Circuits and Systems Conference. Bratislava, September 4-5, 1997.
  7. Multi-Valued Simulation of Digital Circuits (R.Ubar). 21st International Conference on Microelectronics. Nis, Yugoslavia, September 14-17, 1997.
  8. Behavioral Level Modeling of Digital Systems for Testing Purposes (R.Ubar). 42nd International Conference, Ilmenau (Germany), September 22-25, 1997.
  9. Automatic Test Generation System for VLSI (G.Jervan, A.Markus, J.Raik, R.Ubar). 1st Electronic Circuits and Systems Conference. Bratislava, September 4-5,1997, pp. 255-258.
  10. A Set of Tools for Estimating Quality of Built-In Self-Test in Digital Circuits (G.Jervan,  A.Markus, P.Paomets, J.Raik, R.Ubar). Proc. of the International Symposium on Signals, Circuits and Systems. Iasi, (Romania), October 2-3, 1997, pp.362-365.
  11. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments  (A.Benso, P.Prinetto, M.Rebaudengo, M.Sonza Reorda, J.Raik, R.Ubar). 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Paris, October 20-22, 1997, pp. 212-216.
  12. Assembling Low-Level Tests to High-Level  Symbolic Test Frames (G. Jervan, A.Markus, J. Raik, R. Ubar). IEEE 15th NORCHIP Conference, Tallinn, November 10-11, 1997, pp. 275-280.
  13. Mixed-Level Test Generator for Digital Systems (M.Brik, G.Jervan, A.Markus,  P.Paomets,  J.Raik, R.Ubar). Proceedings of the Estonian Acad. of Sci. Engng, 1997, Vol. 3 , No 4, pp. 271-282.

1996

  1. Education Environment for Electronics and Microsystems (M.Ajaots, M.Min, T.Rang, R.Ubar). Proc. of the First European Workshop on Microelectronics Education. Villard de Lans, France, February 5-6, 1996, p.39.
  2. Low-Cost CAD Software for Teaching Digital Test (R.Ubar, P.Paomets, J.Raik). Proc. of the First European Workshop on Microelectronics Education. Villard de Lans, France, February 5-6, 1996, p.48.
  3. Test Synthesis with Alternative Graphs (R.Ubar). IEEE Design and Test of Computers. Spring, 1996, pp.48-59.
  4. Teaching Test and Design for Testability with TURBO-TESTER Software (G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar). Proc. of the 3rd Workshop on Mixed Design of Integrated Circuits and Systems, Lodz, May 1996, pp. 589-594.
  5. Combining Symbolic Techniques with Topological Approach in Test Generation (R.Ubar). Proc. of the 3rd Workshop on Mixed Design of Integrated Circuits and Systems, Lodz, May 1996, pp. 377-382.
  6. Multi-Level Test Generation and Fault Diagnosis for Finite State Machines (R.Ubar, M.Brik). Lecture Notes in Computer Science No 1150. Dependable Computing - EDCC-2. Springer-Verlag, 1996, pp.264-281.
  7. Education Environment for Electronics and Microsystems (M.Ajaots, M.Min, T.Rang, R.Ubar). Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. 1996, p.145-148.
  8. Low-Cost CAD System for Teaching Digital Test (R.Ubar, P.Paomets, J.Raik). Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. 1996, p.185-188.
  9. Electronics as Infrastructure of the Innovation in Estonia (M.Min, T.Rang, R.Ubar). Congress of Estonian Scientists, Tallinn, 1996, pp.265.
  10. Fault Model and Test Synthesis for RISC Processors (R.Ubar, A.Markus, G.Jervan, J.Raik). Baltic Electronics Conference. Proceedings. Tallinn, October 7-11, 1996, pp. 229-232.
  11. Test Generation for Finite State Machines (R.Ubar, M.Brik). Baltic Electronics Conference. Proceedings. Tallinn, October 7-11, 1996, pp. 233-236.
  12. A Constraint-Driven Gate Level Test Generation (J.Raik, R.Ubar, G.Jervan,    H.Krupnova). Baltic Electronics Conference. Proceedings. Tallinn, October 7-11, 1996,  pp. 237-240.
  13. Electronics Competence Centre and Research in Digital Test at Technical University of Tallinn (R.Ubar). Invited paper. IEEE 14th NORCHIP Conference, Helsinki, November 4-5, 1996, pp.134-141.

1995

  1. 131. New Curricula and a Competence Centre through TEMPUS at the Technical University of Tallinn (M. Glesner, T. Hollstein, B. Courtois, P. Amblard, R. Ubar, K. Vainomaa). Proc. EC Workshop on Design Methodologies for Microelectronics, Smolenice, 1995,  pp. 347-353.
  2. 132. Hierarchical Test Generation Based on Alternative Graph Model (R. Ubar). Proc. of  2nd  Workshop on Hierarchical Test Generation, Duisburg, 1995.
  3. 133. Case Study in Testing Digital Systems. Invited paper (R. Ubar). Baltic Electronics, Vol. 1, No. 1, Sept. 1995, pp.24-27.
  4. 134. Fault Diagnosis in Digital Devices (R.Ubar). Proceedings of the Estonian Academy of Sciences, Engineering, 1995, No. 1/1, pp.51-67.
  5. 135. Electronics Competence Centre as a Result of European Projects at the Technical University of Tallinn (Ubar). Baltic Electronics, Vol. 1, No. 2, Dec., 1995, pp.9-11.
  6. 136. Hierarchical Test Synthesis for Digital Systems Using Alternative Graph Model. Dagstuhl-Seminar-Report 132, ISSN 0940-1121. Schloss Dagstuhl, 1995, pp.14-15.

1994

  1. Functional Test Program Generation for Digital Systems (R.Ubar,J.Dushina, H.Krupnova, S.Storozhev, V.Zaugarov). Proc. of the 6. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Vaals (Niederlande), March 6-8, pp.14-18, 1994.
  2. Book review (R.Ubar). Boundary-Scan Test. By H.Bleeker, P.Van Den Eijnden and F.De Jong. Kluwer Academic, Boston (1993). 225 pp. In Engineering applications of Artificial Intelligence. Pergamon Press Ltd. 1994.
  3. Test Generation for Digital Systems Based on Alternative Graphs Theory. (R.Ubar). Lecture Notes in Computer Science No 852. Dependable Computing - EDCC-1. Springer-Verlag, 1994, pp.151-164.
  4. Parallel Critical Path Tracing Fault Simulation (R. Ubar). Proc. of the 39. Int. Wiss. Kolloquium. Ilmenau (Germany), Sept. 27-30, 1994. Band 1, pp. 399-404.
  5. Fault Diagnosis of VLSI Devices Using Alternative Graph Representation (R.Ubar). Proc. of The 8th Symposium on Microcomputer and Microprocessor Applications. Budapest, October 12-14, 1994, Volume I, pp.34-44.
  6. A PC-based CAD System for Training Digital Test (R. Ubar, A. Buldas, P. Paomets, J.Raik, V. Tulit). Proc. 5th EUROCHIP Workshop on VLSI Design Training. Dresden, October 17-19, 1994, pp.152-157.
  7. Alternative Graphs as a Mathematical Tool and Knowledge Representation for Diagnosis Purposes in Digital Systems (R. Ubar). Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.
  8. Constraints Analysis in Hierarchical Test Generation for Digital Systems (H. Krupnova, R. Ubar). Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.
  9. Hierarchical Test Generation for Finite State Machines (M. Brik, R. Ubar). Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.
  10. A CAD System for Teaching Digital Test (J. Raik, P. Paomets, E. Ivask, R. Ubar). Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.
  11. Electronics Competence Centre at the Tallinn Technical University. (R.Ubar, K.Vainomaa).Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.

1993

  1. FTGEN - A System for Functional Test Generation (R.Ubar, J.Dushina, V.Zaugarov, E.Krupnova, S.Storozhev). Proceedings of CAD-93: New Information Technologies for Science, Education and Business. Yalta May 4-13, 1993, pp.123-125 (in Russian).
  2. Functional Level Testability Analysis for Digital Circuits (R.Ubar, K.Kuchcinski). Proc. of European Test Conference ETC'93, Rotterdam, April 19-22, 1993, pp.545-546.
  3. Test Generation System for Microprocessors (R.Ubar, J.Dushina,V.Zaugarov, E.Krupnova, S.Storozhev). Proc. of Int. Conf. "Technical Diagnostics-93", St.-Peterburg, June 8-10, 1993, pp.87-89 (in Russian).
  4. Laboratory Course for Training "Digital Design and Test" (R.Ubar,V.Tulit, A.Buldas, M.Saarepera). Proc.of IV EUROCHIP Workshop on VLSI Design Training, Toledo, Sept.30-Oct.2, pp. 112-117, 1993.
  5. TURBO TESTER. A Set of  Software  Tools  for  CAD  of  Test  for  Digital Circuits (R.Ubar, V.Tulit, A.Buldas, M.Saarepera). Proc.of IV EUROCHIP Workshop on VLSI Design Training, Toledo, Sept.30-Oct.2, pp. 396, 1993.
  6. Alternative Graph Based Test Design in Digital Systems. Invited paper. (R.Ubar). Proc. of the 11. NORCHIP Seminar, Trondheim (Norway), Nov. 9-10, pp.48-62, 1993.

1992

  1. Alternative graphs and test pattern design in digital systems. (R. Ubar). Proc. of the 6th Workshop on new directions for testing, Montreal, Canada, May 20-22, 1992.
  2. Multi-Level Test Generation and Fault Diagnosis in Digital Systems. (R. Ubar). Research Report, TIM3/IMAG/INPG, France, 1992, 88 p.
  3. Diagnostic Software for Systems. In "Concise Encyclopedia of Software Engineering" (R.Ubar). Pergamon Press,1992, pp.101-106.
  4. Testing of systems using software. In "Concise Encyclopedia of Software Engineering" (R.Ubar). Pergamon Press,1 992, pp.354-357.
  5. CAD für Digitaltechnik - Eine Programmfamilie für den Entwurf von Testmustern zum Test von Digitalschaltungen (R. Ubar). IBM Hochschulkongress'92. Offene Grenzen - offene Systeme. Dresden 1992, S. IV9 1-14.
  6. Algorithms of Functional Level Testability Analysis for Digital Circuits. (R.Ubar, K.Kuchcinski). Periodica Polytechnica Ser. El. Eng., Vol.36, No.3-4, pp.295-308, 1992.
  7. Functional Level Testability Analysis for Digital Circuits (R.Ubar). Research Report LiTH-IDA-R-92-03, Linkoping University, Sweden, 1992, pp.16.

1991

  1. Digital test design based on alternative graphs. (R.Ubar). Proc. of the 2nd European Design Automation Conference, Amsterdam, February 25-28, 1991.
  2. Test generation of digital systems at functional level. (R.Ubar, K.Kuchcinski, Z.Peng). The 2nd European Test Conference, Munich, Germany, April 10-12, 1991.
  3. New test design techniques for fault detection in digital devices. (R.Ubar). Proc. of the Int. Design Automation Conference APK'91, Kaunas, June, 1991
  4. A set of tools for diagnosis of digital devices. (T.Lohuaru, R.Ubar). PC World, Information Computer Enterprise, Moscow, No1, 1991, pp.122-125 (in Russian).
  5. Fault simulation in digital systems using alternative graphs. (R.Ubar). 36. Int. Wiss. Koll., TH Ilmenau, Oct. 21-24 1991. pp.737-742.
  6. Test generation for ASICs. (R. Ubar). The 1st Finnish-Estonian Workshop on Digital        Circuits and Algorithms, Tallinn, Estonia, March 18-20, 1991.
  7. Digital test design based on alternative graphs. (R. Ubar). The 1st Finnish-Estonian Workshop on Digital Circuits and Algorithms, Tallinn, Estonia, March 18-20,1991.

1990

  1. Test System for Fault Detection and Diagnosis in Microprocessor Control Devices. (T.Lohuaru, M.Mannisalu, P.Pukk, R.Ubar, E.Vanamolder). Proc. of Tallinn Technical University, No.708, 1990, Tallinn, pp.70-84.
  2. New Test Design Techniques for Fault Detection in Digital Objects. (V.Alango, T.Kont, R.Ubar). Proc. of Tallinn Technical University, No. 708, 1990, Tallinn, pp.52-69.
  3. Test Generation for Digital Systems at Functional Level. (K.Kuchcinski, Z.Peng, R.Ubar). Research Report LiTH-IDA-R-90-06, Linkoping University, Sweden, 1990, pp.21.
  4. An approach to develop intelligent digital test systems. (R.Ubar). Periodica Polytechnica Ser. Electrical Engineering, Vol.34, No.4, pp.233-244, 1990.

1989

  1. Functional Level Test Set Generation Methods. Invited paper. (R. Ubar). Proc. of the 12th Conf. on Fault-Tolerant Systems and Diagnostics, Prague, Sept.,1989, pp.46-55.
  2. Multi-Valued Simulation on the Alternative Graph Model of Digital Devices. (R.Ubar and A.Voolaine). Proc. of the 12th Conf. on Fault-Tolerant Systems and Diagnostics, Prague, Czechoslovakia, September, 1989, pp.101-104.
  3. Generation of Test Experiments for Digital Devices. (A.Toomsalu, R.Ubar, V.Zaugarow). Proc. of the 9th Int. Conf., Mittweida, Germany, September, 1989, pp.46-54.
  4. Automatic Test Program Generation System for Digital Systems. (V.Alango, T.Kont, R.Ubar). Proc. of the 1st Int. Conf.on CAD of Digital Systems, Leningrad, 1989, pp.23-31 (in Russian).
  5. Probabilistic Testing Digital Circuits using Alternative Graphs. (R.Ubar). Proc. of Tallinn Technical University, No.696, 1989, Tallinn, pp.89-96 (in Russian).
  6. Functional Specification and Testing of Digital Systems. (R.Ubar). Proc. of the 3rd Symp Multimicroprocessor Systems Vol.1, Stralsund, Germany, October, 1989, pp.207-217.
  7. Ein universeller Weg zur Automatisierung des Testentwurfs für digitale Objekte (R. Ubar, T. Lohuaru). In “Fehler in Automaten” von D. Bochmann und R. Ubar, VEB Verlag  Technik Berlin, 1989. S. 16-30.

1988

  1. Test Generation for Microprocessors on Alternative Graphs. (R. Ubar). Proc. The 33rd Int. Conference, Technical University of Ilmenau, October, 1988, pp.11-14 (in German).
  2. Description of Digital Objects with Alternative Graphs for Test Generation Purposes. (T.Lohuaru and R.Ubar). Proc. of the 11th Conf. on Fault-Tolerant Systems and Diagnostics, Suhl, May 1988, pp.157-163.
  3. Test Program Compilation in Automated Test Generation for Microprocessors. (V.Alango, T.Kont, R.Ubar). Proc. of Tallinn Technical University, No.674, 1988, Tallinn, pp.78-87  (in Russian).
  4. Test Generation for Data Parts in Digital Systems. (G.Elst, T.Lohuaru, B.Straube, R.Ubar). Proc. of Tallinn Technical University, No.674,1988, Tallinn, pp.65-77 (in Russian).
  5. Alternative Graphs and Technical Diagnosis of Digital Devices. (R. Ubar). Electronic Techniques, Vol.8, No.5 (132),1988, Moscow, pp.33-57 (in Russian).
  6. Integrated CAD of Testable Digital Systems for PCs. (V. Grigorenko, T. Lohuaru, R. Raud, R. Ubar). Proc. of. 5th International Workshop on Automation and Scientific Instrumentation (ASI’88), Varna, October 11-21, 1988, pp. 250-256 (in Russian).

1987

  1. About Test Synthesis for Microprocessor VLSI. (T.Lohuaru and R.Ubar). Journal of Design and Diagnostics of Computers, Institute of Cybernetics, Tallinn, 1987, pp.30-42 (in Russian).
  2. Test Generation for Microprocessor Control Mechanisms.(R.Ubar). Proc. of the 10th Conf. on Fault-Tolerant Systems and Diagnostics, Varna, Bulgaria, September, 1987, pp. 305-311.

1986

  1. General  Approach to Solving Diagnosis Tasks for Digital Systems. (T.Lohuaru, R.Ubar, T.Evartson). Proc. of the 9th All-Union Symposion on Redundancy in Information Systems, Leningrad, May, 1986, pp.32-35 (in Russian).
  2. Research and Development of Testing Methods for Digital Systems (R. Ubar). Thesis of Dr.Sc. Dissertation, Riga, 1986, 43 pp. (in Russian).
  3. Description of Microprocessor LSI by Alternative Graphs.(R. Ubar). Proc. of Technical Diagnosis Conference, Rostow-at-Don, USSR, May, 1986, pp.24-30 (in Russian).
  4. Methods of Testing Digital Systems. (R. Ubar). Proc. of  Tallinn Technical University, No.626, 1986, Tallinn, pp.61-73 (in Russian).
  5. Research and Development of Testing Methods for Digital Systems. (R.Ubar) DSc Dissertation. Institute of Electronics and Computer Science, Riga, 1986, 496p.

1985

  1. About Simulation of Long Input Sequences for Digital circuits with Counter Structures. (T. Evartson and R.Ubar). Proc. of Tallinn Techn. University, No.601, 1985, Tallinn, pp.61-74 (in Russian).
  2. Using Alternative Graphs for Automatization of Test Program Synthesis for Microprocessor LSI. (R. Ubar), Electronic Techniques Ser.8, 1985, Vol.5 (116), Moscow, pp.110-113.
  3. Generation of Universal Tests for Digital Devices by Alternative Graphs. (R. Ubar). Proc. of Tallinn Techn. University, No.601, 1985, Tallinn, pp.51-60 (in Russian).
  4. Testverfahren ftr Assembler-Programme. (T.Lorenz, G.Knospe, R.Ubar). Proceedings of The Ingenieurhochschule Wismar, No4, 1985, s.8-19 (in German).

1984

  1. General Approach to Test Synthesis for Digital Circuits and Systems. (R. Ubar). Proc. of  the 10th All-Union Workshop on Technical Diagnostics, Tallinn, Oct., 1984, pp.75-81. (in Russian).
  2. Optimization of Fault Search Processes in Digital Devices. (R. Ubar). Journal of Applied Automata Theory, Humboldt University, Berlin, 1984, pp.71-106 (in Russian).
  3. Fault Localization Control in Digital Circuits with Counters. (T.Evartson, R.Ubar, A.Viilup). Proc. of the 10th All-Union Workshop on Technical Diagnostics, Tallinn, Oct.,1984, pp.28-32 (in Russian).
  4. Computer-Aided Test Generation for Digital Circuits on the Model of Alternative Graphs. (R. Ubar). Proc. of  Technical Diagnosis Conference, Rostow-at-Don, May, 1984,   pp.120-127 (in Russian).

1983

  1. General Model of Alternative Graphs for Test Generation in Digital Systems. (R. Ubar), Proc. of  Tallinn Technical University, No.550, 1983, Tallinn, pp.97-109 (in Russian).
  2. Test Pattern Generation for Microprocessor Systems on the Alternative Graph Model. (R. Ubar), Proc. of the 3rd Symp. of the IMEKO Techn. Committee on Technical  Diagnostics. Moscow, 1983, pp.403-410.
  3. Test Generation for Digital Systems on the Vector Alternative Graph Model. (R. Ubar). Proc. of the 13th Annual Int. Symp. on Fault Tolerant Computing, Milano, Italy, 1983, pp.374-377.
  4. Test Generation for Microprocessors. (R. Ubar). Proc. of the 6th Conf. on Fault-Tolerant Systems and Diagnostics, Brno, Czechoslovakia, 1983, pp.209-215.
  5. Automated Test Synthesis for Fault Diagnosis in Digital Devices. (T.Lohuaru, M.Pall, R.Ubar). Journal of Academy of Sciences of Estonia, Vol.32, Phys.& Math., 1983, No.1, pp.84-94 (in Russian)

1982

  1. Generation of Complete Tests for Combinational Circuits. (R.Ubar), Journal of Academy of  Sciences of Estonia, Vol.31, Phys.& Math., 1982, No.4, pp.418-427 (in Russian).
  2. Data Generation In Test  Development for Microprocessors. (A.Toomsalu and R.Ubar), Proc. of Tallinn Technical University, No.530, 1982, Tallinn, pp.63-73 (in Russian).
  3. General Approach to Multi-Valued Simulation of Digital Circuits on Alternative Graphs. (M.Pall, R.Ubar, A.Voolaine). Proc. of Tallinn Technical University, No.530, 1982, Tallinn, pp.23-38 (in Russian).
  4. Optimierte Steuerung der Fehlersuche auf digitalen Leiterplatten. (E.Thoma and R.Ubar), Proc. of  the 27th International Conference, Technical University of Ilmenau, October, 1982, H.3, pp.65-68.
  5. Reducing the Combinatorial Complexity in Test Generation for Digital Automata. (R. Ubar). Proc. of  Tallinn Techn. University, No.550, 1982, Tallinn, pp.111-119 (in Russian).

1981

  1. Vektorielle Alternative Graphen und Fehlerdiagnose für digitale Systeme. (R. Ubar), Nachrichtentechnik/Elektronik, (31) 1981, H.1, pp.25-29.
  2. Optimization of Fault Localization Procedures in Digital Systems. (T.Evartson, R.Ubar), Proceedings of the All-Union Conference on CAD of Computers, Kaunas, June,1981, pp.175-184 (in Russian).

1980

  1. Fault Specification in Digital Devices. (R. Ubar), Proc. of Tallinn Technical University, No.497, 1980, Tallinn, pp.3-9 (in Russian).
  2. Desription of Computers by Vector Alternative Graphs for Diagnostic Microprogram Synthesis. (R. Ubar), Proc. of Tallinn Technical University, No.497, 1980, Tallinn, pp.11-20 (in Russian).
  3. Test Generation for Digital Circuits by Alternative Graphs. (M.Plakk and R.Ubar), Automatics and Telemechanics, No.5, 1980, Moscow, pp.152-163 (in Russian).
  4. Fault Localization in Digital Circuits in the Dialogue Mode. (R.Ubar), Proc. of Technical Diagnosis Conference, Rostow-at-Don, May, 1980, pp.76-85 (in Russian).
  5. Test Simulation for Digital Devices on the Alternative-Graph-Model. (R. Ubar), Proc. of the 3rd Conf. on Fault-Tolerant Systems and Diagnostics, Katowice, Poland, 1980.
  6. Beschreibung Digitaler Einrichtungen mit Alternativen Graphen für die Fehlerdiagnose.(R.Ubar), Nachrichtentechnik/Elektronik, (30) 1980, H.3, pp.96-102.
  7. Digital Circuit Test Design using the Alternative Graph Model. (M.Plakk, R.Ubar). Automation and Remote Control, Vol.41, No 5, part 2,  Nov. 1980, Plenum Publishing Corporation, USA, pp. 714-722.
  8. Detection of Suspected Faults in Combinational Circuits by Solving Boolean Differential Equations (R.Ubar). Automation and Remote Control, Vol.40, No 11, part 2,  Nov. 1980, Plenum Publishing Corporation, USA, pp. 1693-1703.

1979

  1. Description of Digital Devices by Alternative Graphs.(R.Ubar), Proc. of Tallinn Technical University, No.474, 1979, Tallinn, pp.11-33 (in Russian).
  2. Synthesis of Test Pairs for Combinational Circuits. (M.Plakk and R.Ubar), Proceedings of Tallinn Technical University, No.474, 1979, Tallinn, pp.45-68 (in Russian).
  3. Aufstellung von Testfolgen für logische Schaltungen. (M.Plakk and R.Ubar), Proc. of  The 24th International Conference, Technical University of  Ilmenau, October, 1979, H.2,  pp.93-96.
  4. Computer-Aided Module-Level Test Generation for Digital Devices on the Basis of their Alternative-Graph Model. (M.Pall and R.Ubar), Preprints of IFAC/IFIP 2nd Int. Symposium, Prague, Czechoslovakia, 1979, v.1, pp. C-XIII-1-4.
  5. Alternative Graphs and Test Generation for Digital Systems. (R. Ubar), Proc. of the 2nd Conf. on Fault-Tolerant Systems and Diagnostics, Brno, Czechoslovakia, 1979, pp.177-184.
  6. Fault Diagnosis in Combinational Circuits by Solving Boolean Differential Equations. (R. Ubar), Automatics and Telemechanics, No.11, 1979, Moscow, pp.170-183 (in Russian).
  7. Fault Diagnosis in Sequential Circuits. (K.Grigorjeva and R.Ubar), Proc. of Tallinn Technical University, No.474, 1979, Tallinn, pp.35-44 (in Russian).
  8. Diagnosis of Combinational Circuits in the Extended Class of Faults. (R. Ubar), Proc. of the Conference on CAD of  Electronic Equipments, Vilnius, June, 1979, pp.177-180 (in Russian).
  9. Minicomputer Software for Fault Localization Control in Digital Circuits. (T.Lohuaru, R.Ubar, A.Viilup), Preprints of IFAC/IFIP 2nd Int. Symposium, Prague, Czechoslovakia,  1979, v.1, pp. P-XIV-1-4.

1978

  1. A Decomposition Method of Fault Diagnosis in Combinational Circuits. (R.Ubar), Proc. of  Tallinn  Technical  University, No.457, 1978, Tallinn, pp.3-22 (in Russian).
  2. Module Level Fault Diagnosis in Combinational Networks. (R.Ubar), Proc. of the 1st Conference on Fault-Tolerant Systems and Diagnostics, Gdansk, Poland, 1978, pp.297-314.
  3. Analysis of Diagnostic Tests for Combinational Circuits by Method of Backtracking of Faults. (R.Ubar). Automation and Remote Control, Vol.40, No.11, part 2, Nov. 1978. Plenum Publishing Corporation, USA, pp. 1254-1260.

1977

  1. Analysis of Diagnostic Tests for Combinational Circuits by the Method  of Fault Backtracing.(R. Ubar), Automatics and Telemechanics, No.8, 1977, Moscow, pp.168-176  (in Russian).
  2. Deductive Fault Analysis in Synchronized Digital Devices  without  Global Feedbacks. (P.Kitsnik, R.Ubar, A.Viilup), Proc. of the All-Union Conf. on CAD of Computers, Kaunas, June, 1977, pp.178-181 (in Russian).
  3. Using Alternative Graphs in Test Synthesis  for  Combinational  Circuits. (M.Plakk and R.Ubar), Proc. of Tallinn Techn. University,  No.432,  1977, Tallinn, pp.3-13 (in Russian).
  4. Formulas  for  Deductive  Analysis  of  Tests  for  Synchronized  Digital Devices.(P.Kitsnik and R.Ubar), Proc. of  Tallinn Technical University,  No.432, 1977, Tallinn, pp.15-23 (in Russian).
  5. Deductive Test Analysis Method for Logic Devices. (P.Kitsnik, R.Ubar, A.Viilup), Proc. of  Technical Diagnosis Conference, Rostow-at-Don, May, 1977, pp.46-51 (in Russian).
  6. Deductive Fault Analysis in Sequential Circuits. (R. Ubar), Proc. of  Int. Conference on Technical Diagnostics, Praha, Czechoslovakia, 1977, pp.189-192 (in Russian).
  7. Berechnung von Boole'schen Ableitungen bei der Testsatzanalyse für digitale Schaltungen. Nachrichtentechnik/Elektronik, 1977, H.1, s.21-23.
  8. Multiple Fault Analysis in Logic Circuits. (R. Ubar), Proc. of the IFAC Symposium on Discrete Systems, Dresden, 1977, Band 4, pp.48-57.
  9. Fault Localization in Digital Circuits with Automatic Test Equipments. (T.Lohuaru, R.Ubar, A.Viilup), Proc. of Tallinn Technical University, No.432, 1977, Tallinn, pp.37-45 (in Russian).

1976

  1. Equivalent Transformations of Diagnostic Dictionaries. (R. Ubar), Journal of Bauman Technical University  of  Moscow,  No.210,  1976,  Moscow,  (in Russian).
  2. Test Generation for Digital Circuits with Alternative Graphs. (R.  Ubar), Proceedings of Tallinn Technical University, No.409, 1976, Tallinn, pp.75-81 (in Russian).
  3. About General Definition of the Diagnosis Problem for  Digital  Circuits, (R. Ubar), Proceedings  of  Tallinn  Technical  University,  No.409, 1976, Tallinn, pp.69-73 (in Russian).
  4. Ein Deductives  Verfahren zur Testsatzanalyse für  digitale  Schaltungen, (R. Ubar), Proc. of Ingenieurhochschule Dresden No.1, 1976, Dresden.
  5. Über einige Probleme der Testsatzanalyse für digitale Systeme (R.  Ubar), Proceedings of Technical University Dresden, No.3,  1976,  Dresden.
  6. Simulating System for Minicomputer Diagnostic Programs. (P.  Kitsnik,  R. Ubar, A.Viilup),  Preprints of IFAC/IFIP 1st Int.  Symp.,  Tallinn, August, 1976, pp.115-117.
  7. Berechnung von Tests für die  Fehlerdiagnose  in  digitalen  Systemen.(R. Ubar), Proc. of  21.  Int. Wiss. Koll., Technical University of Ilmenau, October, 1976, pp.33-35.

1973

  1. Diagnosis of Multiple Faults in Combinational Circuits.  (U.  Heiter,  R. Ubar, A. Viilup), Proceedings of Tallinn Techn. University, No.350, 1973, Tallinn, (in Russian).
  2. Synthesis of Test Procedures for Complex Technical Objects, (B. Dobritza, R. Ubar), Journal of Bauman Technical University of Moscow, No.162, 1973, Moscow, (in Russian).

1971

  1. About Selection of  Test  Points.  (R.  Ubar),  Automatics  and  Computer Engineering, No.3, 1971, Riga, (in Russian).
  2. Using  Monte-Carlo  Method  for  Optimization  of  Test  Processes.  (V. Maslennikow, R.  Ubar),  Proceedings  of  Bauman  Technical  University, No.148, 1971, Moscow, (in Russian).
  3. Minimization of Average Time of Fault Detection  Processes  in  Technical Devices. (V. Maslennikow,  R.  Ubar),  Proceedings  of  Bauman  Technical University of Moscow, No.148, 1971, Moscow, (in Russian).
  4. Choice of Controlled Parameters (R.Ubar). Plenum Publishing Corporation, 1971, USA, pp. 27-31.

1970

  1. About a Scheduling Task in Time Domain (R.Ubar). Proceedings of Tallinn Technical University, No 291, 1970 (in Russian).

1968

  1. About Minimization of the Test Length for Complex Technical Systems (R. Ubar). Proc. of the All-Union Conference “Applications of the Information Theory”, Moscow, 1968 (in Russian).

Patents in USSR

  1. Equipment for Testing LSI. (T. Lohuaru and R.Ubar), A.C. No.1218390, Inf. Bulletin  No.10, 1986.
  2. Equipment  for  Testing  Synchronized  digital   circuits.  (T.Evartson, R.Ubar, A.Viilup), A.C. No.3772884/24, Inf. Bulletin No.25, 1986.
  3. Equipment for Fault Localization in Digital Objects. (T.Evartson, H.Haak, T.Lohuaru, R.Ubar), A.C. No.3984709/24, Inf. Bulletin No.19, 1987.
  4. Equipment for testing  VLSI.  (T.Lohuaru,  M.Mannisalu,  P.Pukk,  R.Ubar,  E.Vanamolder). A.C. No. SU 1652976 A1, Inf. Bulletin No.20, 1991.