First IEEE International Workshop on
Testing Three-Dimensional Stacked Integrated Circuits
3D-Test
in conjunction with ITC / Test Week 2010
November 4-5, 2010 - Convention Center - Austin, Texas, USA
First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-TEST

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

The 2010 edition of the workshop was a big success. The final program can be found here: Final Program

There will be a JETTA Special Issue on 3D-Testing. Please download Call for Papers

In 2011 the workshop will take place in conjunction with ITC-2011, in the Disney Hotel in Anaheim, California, September 22-23, 2011.

 

Further Information:
Yervant Zorian - General Chair
Synopsys
47100 Bayside Parkway
Fremont, CA 94538, USA
Tel.: +1 (510) 360-8035
Fax: +1 (510) 360-8078
E-mail: zorian@synopsys.com

Erik Jan Marinissen - Program Chair
IMEC vzw
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +32 (0)16 28-8755
Fax: +32 (0)16 28-1515
E-mail: erik.jan.marinissen@imec.be

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