First IEEE International Workshop on
Testing Three-Dimensional Stacked Integrated Circuits
in conjunction with ITC / Test Week 2010
November 4-5, 2010 - Convention Center - Austin, Texas, USA

The final program can be downloaded here: (pdf)


Thursday November 4, 2010

 Session 1: Opening

Moderator: Mike Ricchetti - AMD, USA

16:00h: Welcome Address
             General Chair: Yervant Zorian - Synopsys, USA
             Program Chair: Erik Jan Marinissen - IMEC, B

16:15h: Keynote Address:
             Testing in a New Dimension

             Bob Patti - Tezzaron Semiconductor, USA

3D circuit integration offers a new level of system integration. The number of transistors on a chip can be doubled, quadrupled, or more; new process and function mixes, previously at the bleeding edge of possibility, can now become mainstream. The ability to mix technologies at the micron scale opens doors to system miniaturization and new architectures, an advance as revolutionary as the shift from transistors to integrated circuits. However, 3D also demands new testing techniques. It extends the continuing need to test and verify ever more transistors, but it also requires the testing of disparate component types such as integrated analog, sensors, DRAM, Flash, and power supplies, all in the same integrated circuit. Many functions may be hidden from typical test access connections, and some might not be readily testable in their normal modes of operation. New, innovative, compact testing schemes are called for and more robust methods for self test will be required. This presentation will examine current 3D efforts and the direction of 3D integration. It will also look at some of the methods currently being employed to improve testability, self test performance, and self-repair.


Session 2: 3D Design-for-Test

Moderator: Stephen Pateras - Mentor Graphics, USA

17:00h: Invited Address:
             An Integrated Approach to Design and Test of 3D ICs

             Brion Keller  - Cadence Design Systems, US

As 3D stacking drives new design and integration methodologies, the manufacturing test aspects
must be considered early on in the design phase to ensure high testability and predictability, both
at the die/wafer tier level and final package testing. Among other things, this requires a framework
to both model the complex interactions between design and test as well as enable quick trade-offs between different DfT architectures and partitioning decisions. This talk will outline the key integration challenges and innovative approaches to address these challenges with high predictability.


17:30h: Embedded Test Resource Partitioning for Memories in a 3D-IC Context
             Yervant Zorian - Synopsys, USA

17:45h: Functional/Structural Test Boundaries for 3D-IC
             Rob Aitken, Teresa McLaurin, Sachin Idgunji - ARM, USA

18:00h: Standardization for 3D-Testing
             Erik Jan Marinissen - IMEC, B

18:15h: Mini-Panel


Session 3: Posters and Demos

18:30h:  For list of Posters and Table-Top Demos: see Posters and Table-Top Demos.


Workshop Reception



Friday November 5, 2010

Workshop Breakfast


Session 4: Pre- and Post-Bond Testing

Moderator: Tapan Chakraborty - Alcatel-Lucent, USA

08:00h: KGD Probing of TSVs at 40um Array Pitch
             Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Chris Fournier,
             Eric Strid - Cascade Microtech, USA

08:30h: Sharing of Logic and Test TSVs for Testing of 3DICs
             Shravan Garlapati, Michael S. Hsiao, Leylay Nazhandali -
             Virginia Tech, USA

09:00h: Applying Electric Fault Simulation for Deriving Tests for TSVs
             Matthias Gulbins, Fabian Hopsch, Peter Schneider, Bernd Straube,
             Wolfgang Vermeiren - Fraunhofer IIS/EAS, D

09:30h: Impact of Various Test Flows on the Cost in 3D D2W Stacking
             Mottaqiallah Taouil, Said Hamdioui - Delft Univ. of Technology, NL;
             Erik Jan Marinissen - IMEC, B


Session 5: Posters and Demos

10:00h:  For list of Posters and Table-Top Demos: see next page.
              Coffee and tea provided.


Session 6: TSV Testing

Moderator: Craig Bullock - Texas Instruments, USA

10:30h:  Comparing Through-Silicon Via Void/Pinhole Defect Self-Test Methods
              Yi Lou, Zhuo Yan, Fan Zhang, Paul Franzon -
              North-Carolina State Univ., USA

11:00h:  Multi-Scale Simulation and Characterization for Stress Management in
              3D IC TSV-Based Integration Technology: Stress Assessment
              for Chip Performance
              Valeriy Sukhavev, Armen Kteyan, Nikolay Khachatryan,
              Henrik Hovsepyan, Jun-Ho Choy - Mentor Graphics, USA;
              Ehrenfried Zschech, Rene Huebner - Fraunhofer IZFP, D

11:30h:  Electrical Tests for Three-Dimensional ICs with TSVs
              Hao Chen, Jian-Yu Shih, Shih-Wei Li, Hung-Chih Lin, Min-Jer Wang,
              Ching-Nen Peng - TSMC, TW


Workshop Luncheon



Session 7: Posters and Demos

13:00h: For list of Posters and Table-Top Demos: see Posters and Table-Top Demos.


Session 8: 3D-SIC Applications and Test

Moderator: Samy Makar - Apple, USA

13:30h: 3D-TSV Technology: A DfT and Test Perspective
             Michael Laisne, Rajamani Sethuram - Qualcomm, USA

13:45h: A Configurable Sheet of Wide I/O Memory for Stacking Under a Variety
             of High-Power ASICs
             Peter M. O'Neill, Chinmay Gupte - Avago Technologies, USA

14:00h: Wide-IO 3D for Multimedia Application Processors: Operational Nightmare?
             Stephane Lecomte - ST-Ericsson, USA

14:15h: From Stacked to 3D Devices
             Vincent Chalendard, Olivier Alavoine, Adin Hyslop, Christophe Sucur,
             Jean-Pierre Gibaux - Texas Instruments, FR


Session 9: Panel Discussion
14:30h: Challenges and Solutions in 3D Wafer Probing

Moderator: Erik Jan Marinissen - IMEC, B

  Marc Loranger - FormFactor, USA
  Wayne Moorhead - Scanimetrics, CAN
  Jay Orbon - Verigy, USA
  Dan Rishavy - TEL, USA
  Ken Smith - Cascade Microtech, USA
Andy Yiin - Intel, USA


16:00h: Workshop Closure


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