Second IEEE International Workshop on
Testing Three-Dimensional Stacked Integrated Circuits
3D-Test
in conjunction with ITC / Test Week 2011
September 22-23, 2011 - Disneyland Hotel Anaheim, California, USA
Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-TEST

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.

In 2012 the workshop will take place in the Disney Hotel in Anaheim, California, November 8-9, 2012.

 

Further Information:
Yervant Zorian - General Chair
Synopsys
700 East Middlefield Road
Mountain View, CA 94043-4033, USA
Tel.: +1 (650) 584-7120
E-mail: yervant.zorian@synopsys.com

Erik Jan Marinissen - Program Chair
IMEC vzw
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +32 (0)16 28-8755
Fax: +32 (0)16 28-1515
E-mail: erik.jan.marinissen@imec.be

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