Sixth IEEE International Workshop on
Testing Three-Dimensional Stacked Integrated Circuits
3D-Test
in conjunction with ITC / Test Week 2015
October 8-9, 2015 - Disneyland Hotel Anaheim, California, USA
Program Committee

S. Adham - TSMC (CAN)
V. Agrawal - Auburn Univ. (US)
S. Bhatia - Oasys (US)
K. Chakrabarty - Duke Univ. (US)
S. Chakravarty - Avago Technologies (US)
E. Cormack - DfT Solutions (UK)
A. Cron - Synopsys (US)
A. Crouch - Asset Intertech (US)
P. Franzon - NC State Univ. (US)
S. Hamdioui - TU Delft (NL)
M. Higgins - Analog Devices (IRL)
C.-L. Hsu - ITRI (TW)
M. Hutner - Teradyne (CAN)
L. Jiang - Shanghai JT Univ (CN)
H. Jiao - TU Eindhoven (NL)
H. Jun - SK hynix (KR)
S. Kameyama - Fujitsu (JP)
M. Knox - IBM (US)
M. Laisne - Qualcomm (US)
C.M. Li - NTU (TW)
M. Loranger - FormFactor (US)
A. Majumdar - Xilinx (US)
T.M. Mak - GlobalFoundries (US)
T. McLaurin - ARM (US)
B. Nadeau-Dostie - Mentor Graph. (US)
B. Noia - AMD (US)
C. Papameletis - Cadence (US)
R. Parekhji - Texas Instruments (IN)
B. Patti - Tezzaron Semiconductor (US)
M. Ricchetti - AMD (US)
S. Shaikh - Broadcom (US)
K. Smith - Cascade Microtech (US)
R. Vallauri - Technoprobe (IT)
P. Vivet - CEA-Leti (FR)
M. Wahl - Univ. Siegen (DE)

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