Sixth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-Test 2015

Sixth IEEE International Workshop on
Testing Three-Dimensional Stacked Integrated Circuits

3D-Test

in conjunction with ITC / Test Week 2015
October 8-9, 2015 - Disneyland Hotel � Anaheim, California, USA

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Submission

Submission Instructions

All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Selected submissions can be accepted for regular or poster presentation at the Workshop.

Key Dates

Submission deadline:August 21, 2015
Notification of acceptance: September 4, 2015
Camera-ready material: September 20, 2015

Submissions must be sent in via the Welcome paper submission system: http://welcome.molesystems.com/tttc/3DTEST/2015

Submissions must be sent in as PDF file. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages).