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A New Approach to Build a Low-Level
Malicious Fault List Starting from High-Level Description
and Alternative Graphs (A. Benso, P.Prinetto,
M.Rebaudengo, M.Sonza, R.Ubar). Proc. IEEE European
Design & Test Conference, Paris, March 17-20,
1997, pp. 560-565. |
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Formalization and Validation of the
Std_Logic-1164 and Numeric-Std VHDL Packages using the
Nqthm Theorem Prover (J.Dushina, D.Borrione). Proc. of
the 2nd Workshop on Libraries,
Component Modeling, and Quality Assuarance. Toledo
(Spain), April, 1997, pp. 169-180. |
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Multi-Valued Simulation with Binary
Decision Diagrams (R.Ubar, J.Raik). Proc.IEEE European
Test Workshop, Cagliari (Italy), May 28-30, 1997,
pp.28-29. |
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Representing Transparency Conditions
in Test Generation for VLSI by Decision Diagrams
(R.Ubar). 1st Electronic
Circuits and Systems Conference. Bratislava,
September 4-5, 1997, pp.213-216. |
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Behavioral Level Modeling of Digital
Systems for Testing Purposes (R.Ubar). 42nd
International Conference. Part 1. Ilmenau (Germany),
September 22-25, 1997, pp. 510-515. |
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Exploiting High-Level Descriptions for
Circuits Fault Tolerance Assessments (A.Benso,
P.Prinetto, M.Rebaudengo, M.Sonza Reorda, J.Raik,
R.Ubar). 1997 IEEE International Symposium on Defect
and Fault Tolerance in VLSI Systems. Paris, October
20-22, 1997, pp. 212-216. |
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CAD Software for Digital Test and Diagnostics
(G.Jervan, A.Markus, P.Paomets,J.Raik, R.Ubar). Proc.
of International Conference on Design and Diagnostics of
Electronic Circuits and Systems. Beskydy Mountains,
Czech Republic, May 12-16, 1997, pp.35-40. |
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Boolean Derivatives and Multi-Valued
Simulation on Binary Decision Diagrams (R.Ubar). 4th
International Workshop on Mixed Design of Integrated
Circuits and Systems. Poznan, June 12-14, 1997,
pp.115-120. |
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A Hierarchical Automatic Test Pattern
Generator Based on Using Alternative Graphs (M.Brik,
G.Jervan, A.Markus, J.Raik, R.Ubar). 4th
International Workshop on Mixed Design of Integrated
Circuits and Systems. Poznan, June 12-14, 1997,
pp.415-420. |
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Automatic Test Generation System for
VLSI (G.Jervan, A.Markus, J.Raik, R.Ubar). 1st
Electronic Circuits and Systems Conference.
Bratislava, September 4-5,1997, pp. 255-258. |
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Multi-Valued Simulation of Digital
Circuits (R.Ubar). Proc. of the IEEE 21st
Int. Conference on Microelectronics. Nis, Yugoslavia,
September 14-17, 1997, pp. 721-724. |
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A Set of Tools for
Estimating Quality of Built-In Self-Test in Digital
Circuits (G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar).
Proc. of the International Symposium on Signals,
Circuits and Systems. Iasi, (Romania), October 2-3,
1997, pp.362-365. |
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A VLSI implementation of RSA and IDEA
encryption engine (A.Buldas, J.Põldre). 15th NORCHIP
Conference, Tallinn, November 10-11, 1997, pp. 281-288. |
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Assembling Low-Level Tests to
High-Level Symbolic Test Frames (G.
Jervan, A.Markus, J. Raik, R. Ubar). IEEE 15th
NORCHIP Conference, Tallinn, November 10-11, 1997,
pp. 275-280. |
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Mixed-Level Test Generator for Digital
Systems (M. Brik, G. Jervan, A. Markus, P. Paomets, J.
Raik, R. Ubar). Proceedings of the Estonian Acad. of
Sci. Engng, 1997, Vol. 3 , No 4, pp. 269-280. |
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Circuit Partitioning Method for FPGAs
(H.Krupnova, G.Saucier). Proceedings of the Estonian
Acad. of Sci. Engng, 1997, Vol. 3 , No 4, pp.
280-291. |