Xilinx Design Summary

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	626	15,360	4%
Number used as Flip Flops	561
Number used as Latches	65
Number of 4 input LUTs	836	15,360	5%
Logic Distribution
Number of occupied Slices	699	7,680	9%
Number of Slices containing only related logic	699	699	100%
Number of Slices containing unrelated logic	0	699	0%
Total Number 4 input LUTs	987	15,360	6%
Number used as logic	836
Number used as a route-thru	83
Number used for Dual Port RAMs	16
Number used for 32x1 RAMs	52
Number of bonded IOBs	55	173	31%
IOB Flip Flops	61
Number of Block RAMs	2	24	8%
Number of GCLKs	3	8	37%
Number of DCMs	2	4	50%
Total equivalent gate count for design	164,245
Additional JTAG gate count for IOBs	2,640

Performance Summary
Final Timing Score:	92885	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	1 Failing Constraint