Sequential optimization techniques are needed at several points within a digital system design flow. Earlier in the process, the sequential circuits are modeled using the formalism of finite state machines (FSMs). Such state-based models express sets of sequential functions, mapping a sequence of inputs to a sequence of outputs. The FSMs are either specified directly by the designer using a hardware description language, or realized via high-level synthesis tools from a more abstract description. Given a behavioral algorithmic specification and a library of functional units, high level synthesis constructs a data path by scheduling operations in the algorithm onto specific time steps and binds them onto appropriate functional units. An FSM (controller) that controls the data path is then automatically constructed.

We should emphasize the fact that the machine decomposition is the organic part of synthesis process. A large FSM must be decomposed into ones for more efficient implementations. The task of decomposition has been a classic problem of discrete system theory for many years. The decomposition of FSM is a topic that waxes and wanes in importance. The fundamental works were done in the 1960s, became less interesting during the era of VLSI, and is becoming more important again with pervasive use of programmable logic and low power applications in digital design. A large hardware behavioral description is decomposed into several smaller ones. One goal is to make the synthesis problem more tractable by providing smaller sub-problems that can be solved efficiently. Another goal is to create descriptions that can be synthesized into a structure that meets the design constraints. In the past, the synthesis focused on quality measures based on area and performance. The continuing decrease in feature size and increase in chip density in recent years have given rise to consider decomposition theory for low power as new dimension of the design process.
Various techniques of FSM decomposition fall broadly into next categories: multiplicative decomposition, wherein the graph of the FSM is embedded into a product of smaller graphs, and additive decomposition, wherein the graph of the FSM is partitioned into node disjoint subsets.
Let’s we have an FSM which need to decompose in a network. The individual (component) machines that make up the overall realization are referred to as sub-machines. The prototype machine corresponds to the machine that was used to define the terminal behavior to be realized. The machine that results as a consequence of the decomposition is called the decomposed machine. Informally, the essence of the decomposition task could be described as follows. Given a prototype FSM description of a desired terminal behavior, the decomposition problem is to find sub-FSMs which, when interconnected in a prescribed way, will display that terminal behavior.
We distinguish three methods of decomposition.

In the first method, each sub-machine corresponds to a partition on the set of states (a partition on the set of states, S, in a machine is a collection of disjoint subsets of states whose set union is S). All the states belonging to a single block in a submachine are given the same code in that submachine. Therefore, there is no way of distinguishing between two states belonging to a single block in a submachine without recourse to information from other sub-machines. A block of states in a partition effectively corresponds to a state in the submachine associated with that partition. The functionality of the prototype machine is maintained in the decomposed machine if the partitions associated with the decomposition are such that their product is the zero-partition on S (every block of partition consists exactly of one state).

The idea of the second method is to introduce additional “idle” states into the sub FSMs. The network of FSMs consists of components working alternatively in time, i.e. all components except one are suspended in one of extra state (the “wait” state). The network of interacting sub-FSMs corresponds to a given partition on the set of states of prototype FSM. The number of sub-FSM in the network is equal to the number of blocks and the number of states of sub-FSM is equal to the number of states in corresponding block of given partition plus 1 (wait state).

The third method of decomposition proceeds from a given cover (not a partition) on the set of states of prototype FSM. Each sub-machine corresponds to a subset of the set of states of prototype FSM. This method is generalization of the previous one (more than of machines could be active executing a computation at any given time while the other sub-FSMs are idle).


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  1. S. Devadze, M. Kruus, and A. Sudnitson, “Web-Based Software Implementation of Finite State Machine Decomposition for Design and Education”, in Proc. International Conference on Computer Systems and Technologies (CompSysTech’2001), Sofia, Bulgaria, 2001, v.4, pp. 1-7. (ISBN: 954-9641-25-2)
  2. A. Sudnitson, “Fininite State Machines with Datapath Partitioning for Low Power Synthesis”, in Proc. 8th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES’2001), Zakopane, Poland, 2001, pp.163-168. (ISBN: 83-87202-98-3)
  3. S. Devadze, A. Jutman, M. Kruus, A. Sudnitson, and R. Ubar, “Web Based Tools for Synthesis and Testing of Digital Devices”, in Proc. International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, 2002, v.1, pp. 91-96. (ISBN: 954-9641-287)
  4. E. Fomina, A. Keevallik, M. Kruus, and A. Sudnitson, “Web-based Tools for Finite State Machine Decomposition with Analysis of Information Flows”, in Proc. 8th International Baltic Electronics Conference ( BEC’2002), Tallinn, Estonia, 2002, pp. 165-168. (ISBN: 9985-59-292-1)
  5. A. Jutman, M. Kruus, A. Sudnitson, and R. Ubar “Distance-Learning Tools for Digital Design and Test Issues”, in Proc. 29th International Conference on Information Technologies in Science, Education, Telecommunication, Business (IT+SE’ 2002), Gurzuf, Ukraine, 2002, pp.269-272
  6. E. Fomina, A. Keevallik, M. Kruus, and A. Sudnitson, “A Decomposition Procedure for Register-Transfer Level Power Management”, in Proc. International Conference on Computer Systems and Technologies (CompSysTech’2003), Sofia, Bulgaria, 2003, v.1, pp.21-26. (ISBN: 954-9641-33-3)
  7. A. Jutman, A. Sudnitson, R. Ubar, and H.-D. Wuttke, “Java Applets Support for an Asynchronous-Mode Learning of Digital Design and Test”, in Proc. 4th International Conference on Information Technology Based Higher Education and Training (ITHET 2003), Marrakech, Morocco, 2003, pp.397-401. (ISBN: 9954-8352-0-2)
  8. A. Jutman, A. Sudnitson, and R. Ubar, “Digital Design Learning System Based on Java Applets”, in Proc. 4th Annual Conference of the LTSN Centre for Information and Computer Sciences, NUI Galway, Ireland, 2003, pp.183-187. (ISBN: 0-9541927-4-5)
  9. S. Devadze, E. Fomina, M. Kruus, and A. Sudnitson, “Web-Based System for Sequential Machines Decomposition”, in Proc. IEEE EUROCON 2003 International Conference on Computer as a Tool, Ljubljana, Slovenia, 2003, V. 1, pp. 57-61. (ISBN: 0-7803-7763-X, IEEE Catalog No.:03EX665)


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Last update: 3 August, 2004