IAS0600 Digital Systems Design with VHDL (LABS)

To stimulate the student’s activity a project-based evaluation approach is adopted. Grading consists of control of knowledge in examinations and of the demonstration of the projects and the quality of written reports. 60 points are awarded for passing all the labs, 10 points are awarded for passing intermediate exam on 04.11.2020 and 30 points are awarded for passing the final exam.

Lecturer:

associate professor Alexander Sudnitson

Lab Assistant:

research scientist Dmitri Mihhailov

Lab Syllabus !!! :

[PDF]

Important !!! :

changes in the lab order due to the recent regulation of TalTech rectorate (updated on 07.09.2020) [PDF]

Reports and source files:

dmitri.mihhailov@taltech.ee (cc: aleksander.sudnitson@taltech.ee)
[MAILTO]

Results:

[LINK]

Useful Links and Materials:
  1. Nexys 4 DDR FPGA Board Reference Manual [PDF]
  2. Nexys 4 DDR FPGA Board Master XDC File [XDC]
  3. Installing Vivado and Digilent Board Files [LINK]
  4. Getting Started with Vivado [LINK]
  5. Getting Started with the Vivado IP Integrator [LINK]
  6. Vivado Tutorial [PDF]
  7. Xilinx Vivado IDE User Guide [PDF]

 

 LABS SET I (Xilinx FPGA-based)

Requirements and Deadlines:

Deadline for passing the lab course is 18.12.2020

All Labs give 60 points to the final grade (each lab gives 10 points)

No points are awarded if the lab is not passed within deadlines (as specified above and in Lab Syllabus)

Additional 5 points (Bonus 1) are awarded if labs 1-4 are passed until 17.11.2020

Additional 5 points (Bonus 2) are awarded if labs 1-6 are passed until 18.12.2020

Intermediate exam is conducted on 04.11.2020 in ICT-507 at 14:00

Tasks:
  1. (02.09.2020) Labs Overview [PPT]
  2. (09.09.2020, 16.09.2020) Basic Vivado Tutorial : Part 1 [PPT] Part 2 [PPT]
  3. (23.09.2020) Lab 1 : Comparator [PDF] Appendix [PDF]
  4. (07.10.2020) Lab 2 : Adder [PDF]
  5. (21.10.2020) Lab 3 : Counter [PDF] Appendix [PDF]
  6. (04.11.2020) Lab 4 : Creeping Line [PDF]
  7. (18.11.2020) Lab 5 : Parameterizable Multiplier [PDF] Appendix [PDF]
  8. (02.12.2020) Lab 6 : Finite State Machine with Datapath [PDF] Appendix [PDF]

Projects:
  1. RISC Processor [PDF] Example [PDF] MIPS Processor Tutorial [LINK]