IAY0600 Digital Systems Design (LABS)

To stimulate the studentís activity a project-based evaluation approach is adopted. Grading consists of control of knowledge in examinations and of the demonstration of the projects and the quality of written reports (40 points in final grade for doing compulsary labs, up to 80 points in final grade for doing optional labs).

Lecturer:

associate professor Alexander Sudnitson

Lab Assistant:

research scientist Dmitri Mihhailov

Tech. Assistant:

early stage research scientist Artjem Rjabov

Lab Syllabus !!! :

[PDF]

Reports and source files:

dmitri.mihhailov@ttu.ee (cc: aleksander.sudnitson@ttu.ee)
[MAILTO]

LAB defense booking:

Group A (Wednesday)

[WEEK3] [WEEK4] [WEEK5] [WEEK6] [WEEK7] [WEEK8] [WEEK9] [WEEK10] [WEEK11] [WEEK12] [WEEK13] [WEEK14] [WEEK15] [WEEK16]


Group B (Wednesday)

[WEEK3] [WEEK4] [WEEK5] [WEEK6] [WEEK7] [WEEK8] [WEEK9] [WEEK10] [WEEK11] [WEEK12] [WEEK13] [WEEK14] [WEEK15] [WEEK16]

Results:

[LINK]

LABS SET I (Xilinx FPGA-based)

Requirements and Deadlines:

Tutorials are optional

Labs 2-5 are compulsory

Nominal deadline for Labs 2-5 is 16th week

All compulsary Labs give 40 points to the final grade

Labs 6-9 are optional

Nominal deadline for optional Labs 6-9 is 16th week

Optional Lab 6 gives additional 10 + 10 points to the final grade

Optional Lab 7 gives additional 10 points each to the final grade

Optional Lab 8 gives additional 5 points each to the final grade

Optional Lab 9 gives additional 5 points each to the final grade

Tasks:

  1. Tutorials: Vivado [PDF]
  2. Comparator [PDF]
  3. Adder [PDF]
  4. Parameterizable Adder [PDF]
  5. Serial Adder [PDF]
  6. Finite-State Machine: FSM Synthesis [PDF] and Low Power (optional) [PDF]
  7. Greatest Common Divisor [PDF]
  8. Creeping Line [PDF]
  9. LFSR [PDF]

Appendixes:

  1. Nexys 4 DDR FPGA Board [PDF] [XDC]
  2. Xilinx Vivado IDE User Guide [PDF]

Projects:

  1. RISC Processor [PDF] Example [PDF] MIPS Processor Tutorial [LINK]

LABS SET II (Altera FPGA-based)

Requirements and Deadlines:

Tutorials 1 and 4 are optional

Labs 2-3 are optional

Tasks:

  1. Tutorial [PDF]
  2. VGA Port and PS/2 Mouse Port [PDF]
  3. IR Remote Control and LCD Display [PDF]
  4. System on a Programmable Chip Design (Tutorial) [PDF]Source Files [ZIP]

Appendixes:

  1. DE2-115 Manual [PDF]
  2. Video DAC Manual [PDF]
  3. IR Transmitter Manual [PDF]†† IR Receiver Manual [PDF]
  4. LCD Manual [PDF]

Links:

  1. VHDL Tutorial [LINK]
  2. VGA Timing Information [LINK] [LINK]