October 19, 2017 [10:13]
Gert Jervan is a professor of dependable computer systems at the Department of Computer Systems at Tallinn University of Technology. He is also a Dean at the School of Information Technologies.
He received his M.Sc. degree from Tallinn University of Technology in 1998 and Tech. Lic. and Ph. D. degrees from Linköping University (LIU), Sweden in 2002 and 2005, respectively. He was previously with the Embedded Systems Laboratory
(ESLAB) at Linköping University, Sweden
He has been a coordinator of several national and international research projects, most notably he
belonged to the management committee of the Estonian centre of excellence in research CEBE (Centre for Integrated Electronic Systems and Biomedical Engineering) and was a coordinator of the EU FP7 REGPOT project CREDES (Centre of Research Excellence in Dependable Embedded Systems).
He has been a local coordinator of several EU networks of excellence and other projects, such as EIE-Surveyor, ELLEIEC, SALEIE, KhAI-ERA, IT.EE and many others. Currently he is one of the PIs of the EU Horizon 2020 projects TUTORIAL (Twinning to Strengthen Tallinn University of Technology’s Research and Innovation Capacity in Nanoelectronics Based Dependable Cyber-Physical Systems) and IMMORTAL (Integrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems).
He has been serving of the evaluation committees of the Estonian Science Foundation, Estonian Research Council, EC Directorate-General for Research & Innovation. He is regular reviewer for many journals and program committee member of several conferences. He has organized many international workshops and conferences, most recently EWME 2014 and ReCoSoC 2016.
He is also one of the authors of the Strategic Plans of Tallinn University of Technology 2011-2015 and 2016-2020.
Up to date CV (incl. publications) from the ETIS database (link opens in a new window).
- Dependability and fault tolerance of embedded systems
- Networks-on-Chip (NoCs): system-level design, fault tolerance
- Test and Diagnostics of Digital Systems:
- High-Level Testability and Design for Test (DfT)
- Built-in self-test (BIST) and its different flavors
- SoC & NoC Test
- H2020 project TUTORIAL - Twinning to Strengthen Tallinn University of Technology’s Research and Innovation Capacity in Nanoelectronics Based Dependable Cyber-Physical Systems.
- H2020 project IMMORTAL - Integrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems.
- Previous projects:
- Estonian centre of excellence in research CEBE (Centre for Integrated Electronic Systems and Biomedical Engineering)
- EU FP7 REGPOT project CREDES (Centre of Research Excellence in Dependable Embedded Systems).
- IT.EE - ITEE Digital Connected Economy
- KhAI-ERA - Integrating
the National Aerospace University "KhAI"
into European Research Area
- SALEIE - Strategic ALignment of Electrical and Information Engineering in European Higher Education Institutions (Thematic Network)
- ELLEIEC - Enhancing Lifelong Learning in Electrical and Information Engineering (Thematic Network)
- EIE-Surveyor - Electrical and Information Engineering in Europe (Thematic Network)
- Estonian Science Foundation grant: Test and Fault Tolerance of Network-on-Chip Based Systems. 2006-2009. Accepted proposal (pdf).
- STRINGENT project: Hybrid BIST methodology for complex electronic systems
- Member of SNDFT - Swedish Network of Design for Test Research
- INTELECT project: Testability-Driven Hardware/Software Codesign
- COTEST - Testability Support in a Co-design Environment (Project of the IST Programme)
- VILAB: Microelectronics Virtual Laboratory for Cooperation in Research and Knowledge Transfer
- STES - Self-Test in Embedded Systems
- Publications in the ETIS database
- PhD Thesis: Hybrid
Built-In Self-Test and Test Generation Techniques for Digital Systems,
Linköping University, May 2005, 238 pages. Opponent: Prof. Joao Paulo Teixeira,
- Licentiate thesis: High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems, Linköping University, October 2002, 102 pages. Opponent: Prof. Shashi Kumar, Jönköping University, Sweden.
- Publications 1998-2005 (in the ESLAB database, incl. downloadable documents):
- MSc courses:
- IAF0530 - Dependability and fault tolerance
- IAF0320 - Computer Systems Engineering (until 2014)
- Graduate Student Supervision:
- Ardo Allik, Biooptical signal processing from wearable devices for prevention and early diagnosis of cardiorenal diseases, 2016-...
- Behrad Niazmand, Dependability improvements of NoC-based systems, 2014-...
- Siavoosh Payandeh Azad, Application deployment on MPSoC Architecturesunder dependability and mixed-criticality constraints, 2014-...
- Mairo Leier, Scalable Open Platform for Reliable Medical Sensorics (Laiendatav avatud platvorm usaldusväärsete meditsiiniliste sensorite jaoks), PhD 2016. Now with Tallinn University of Technology.
- Erkki Moorits, Embedded Software Solutions for Development of Marine Navigation Light Systems (Sardtarkvara lahendused valgusnavigatsiooni süsteemide arendusel), PhD 2016. Now with Sabik Marine (Carmanah Technologies).
- Mihkel Tagel, Fault tolerance and reliability of networks-on-chip (Kiipvõrkude veakindlus ja usaldusväärsus). PhD 2012. Now with TD Baltic.
- Master Thesis Supervision:
- Jaanus Alnek, Evaluation of the Impact of the Number of TSVs in 3D NoCs, 2014
- Mehrdad Bagheri Majdabadi, Fault Tolerant Scheduling of Mixed-Critical Applications on Multi-Processor Platforms, 2013
- Zahra Jafari, Scheduling of Systems with Mixed-Criticality Requirements, 2013
- Radomir Shebek, Memory consistency and cache coherency in networks on chip based multi-core systems, 2012
- Mairo Leier, Kehalähedase sensorvõrgustiku süsteemi arendus. Südame rütmi jälgimise süsteem (Body Area Network System Development. Heart Rate Monitoring System), 2010.
- Auli Lepp, Temperatuuri-teadlik testide planeerimine 3D arhitektuuriga kiipidel (Temperature-aware test scheduling for 3D architectures), 2009.
- Deniss Nikiforov. Automatic generation of task graphs. Tallinn University of Technology, 2008.
- Vassili Zdanov. Extraction of task-level parallelism. Tallinn University of Technology, 2008.
- Peeter Mäeker. XY-marsruutimisalgoritmil põhineva kiipvõrgu testimise simulaator (XY-routing algorithm based NoC test simulator). Tallinn University of Technology, 2007.
- Mihkel Tagel. Deterministlik võrguliikluse generaator kiipvõrgu simulaatorile (Deterministic traffic generator for NoC simulator). Tallinn University of Technology, 2006.
- Tatjana Shchenova. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. Tallinn University of Technology, 2005.
- Maksim Jenihhin. Test Time Minimization for Hybrid BIST of Systems-on-Chip Tallinn University of Technology, 2003.
- Yuanhui Sun. Automatic behavioral test generation by using a constraint solver. Linköping University, 2002.
- Previous Teaching (at LiU):
- TDTS43 - Computer Networks and Distributed Systems (Development of lab exercises, lab assistant - 1999, 2000)
- TDDB12 - Concurrent Programming and Operating Systems (Development of lab exercises, lab assistant - 1999)
- TTIT61 - Concurrent Programming and Operating Systems (Course assistant - 2000)
- TDDB63 - Concurrent Programming and Operating Systems (Lab assistant - 2000, 2001)
- TDTS80 - Computer Aided Design of Electronics (Course assistant - 2001)
- TDTS01 - Computer Aided Design of Electronics (Development of lab exercises, course assistant, lecturer - 2002-2004)