Gert Jervan

Gert Jervan is a senior research fellow at the Department of Computer Engineering at Tallinn University of Technology. He received his M.Sc. degree from Tallinn University of Technology in 1998 and Tech. Lic. and Ph. D. degrees from Linköping University (LIU), Sweden in 2002 and 2005, respectively. He was previously with the Embedded Systems Laboratory (ESLAB) at Linköping University, Sweden

He belongs to the management committee of the Estonian centre of excellence in research CEBE (Centre for Integrated Electronic Systems and Biomedical Engineering) and is one of the coordinators of the EU FP7 REGPOT project CREDES (Centre of Research Excellence in Dependable Embedded Systems). Since 2006 he is a member of the Estonian Science Foundation's Expert Commission for Physical Sciences and Engineering.

Previously he was one of the coordinators of the national graduate school in information and communication technologies (2005-2008); prepared and managed the R&D infrastructure development project "Embedded Systems and Components" at the Department of Computer Engineering (2005-2008).

He is a special session chair of the 2010 Diagnostic Services in Network-on-Chips workshop (co-located with DAC 2010). Recently he was serving as a vice program chair of Norchip 2008 (November 17-18, 2008), general chair of the 19th EAEEEIE Annual Conference (June 29 - July 2, 2008) and was one of the organizers of the DATE 2008 Friday Workshop Impact of Process Variability on Design and Test.

Up to date CV (incl. publications) from the ETIS database (link opens in a new window).

Research Interests

• Test and Diagnostics of Digital Systems:
• High-Level Testability and Design for Test (DfT)
• Built-in self-test (BIST) and its different flavors
• SoC & NoC Test
• Fault Tolerant Computer Systems: Reliability, QoS, ...
  
  
• Open PhD student positions at CEBE (Centre for Integrated Electronic Systems and Biomedical Engineering). If interested, please send your CV.

Research Activities

• Estonian Science Foundation grant: Test and Fault Tolerance of Network-on-Chip Based Systems. 2006-2009. Accepted proposal (pdf).

• Previous projects:
  • STRINGENT project: Hybrid BIST methodology for complex electronic systems
  • Member of SNDFT - Swedish Network of Design for Test Research
  • INTELECT project: Testability-Driven Hardware/Software Codesign
  • COTEST - Testability Support in a Co-design Environment (Project of the IST Programme)
  • VILAB: Microelectronics Virtual Laboratory for Cooperation in Research and Knowledge Transfer
  • STES - Self-Test in Embedded Systems

Publications

• Publications in the ETIS database
• PhD Thesis: Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems, Linköping University, May 2005, 238 pages. Opponent: Prof. Joao Paulo Teixeira, IST/INSESC-ID, Portugal.
• Licentiate thesis: High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems, Linköping University, October 2002, 102 pages. Opponent: Prof. Shashi Kumar, Jönköping University, Sweden.
• Publications 1998-2005 (in the ESLAB database, incl. downloadable documents):
• Book chapters.
• Conference papers.
• Technical reports.
• Complete list (1998-2005)
• List of older publications (-1998)

Teaching:

• Undergraduate:
  • IAF0030 - Computer Engineering: Advanced Course I - Fault-Tolerant Computer Systems
  • IAF0042 - Computers II

• Graduate:
  • Thesis proposals (Lõputööde teemad)
  • Graduate studies at DCE
  • CAD tools at DCE

• Graduate Student Supervision:
  • Mihkel Tagel (2006 - ...)
  • Tatjana Shchenova (On maternity leave)
  • Erkki Moorits (2008 - ...)
  • Deniss Nikiforov (2008 - ...)

• Master Thesis Supervision:
  • Auli Lepp, Temperatuuri-teadlik testide planeerimine 3D arhitektuuriga kiipidel (Temperature-aware test scheduling for 3D architectures), 2009.
  • Deniss Nikiforov. Automatic generation of task graphs. Tallinn University of Technology, 2008.
  • Vassili Zdanov. Extraction of task-level parallelism. Tallinn University of Technology, 2008.
  • Peeter Mäeker. XY-marsruutimisalgoritmil põhineva kiipvõrgu testimise simulaator (XY-routing algorithm based NoC test simulator). Tallinn University of Technology, 2007.
  • Mihkel Tagel. Deterministlik võrguliikluse generaator kiipvõrgu simulaatorile (Deterministic traffic generator for NoC simulator). Tallinn University of Technology, 2006.
  • Tatjana Shchenova. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. Tallinn University of Technology, 2005.
  • Maksim Jenihhin. Test Time Minimization for Hybrid BIST of Systems-on-Chip Tallinn University of Technology, 2003.
  • Yuanhui Sun. Automatic behavioral test generation by using a constraint solver. Linköping University, 2002.

• Previous Teaching (at LiU):
  • TDTS43 - Computer Networks and Distributed Systems (Development of lab exercises, lab assistant - 1999, 2000)
  • TDDB12 - Concurrent Programming and Operating Systems (Development of lab exercises, lab assistant - 1999)
  • TTIT61 - Concurrent Programming and Operating Systems (Course assistant - 2000)
  • TDDB63 - Concurrent Programming and Operating Systems (Lab assistant - 2000, 2001)
  • TDTS80 - Computer Aided Design of Electronics (Course assistant - 2001)
  • TDTS01 - Computer Aided Design of Electronics (Development of lab exercises, course assistant, lecturer - 2002-2004)

Membership

• Member of the EU thematic network EIE-Surveyor Managing team
• Member of the European Electronic Chips & Systems Initiative (ECSI)
• Member of the IEEE Computer Society, Test Technology Technical Council. Chair of the Estonian CS Chapter.
• Member of the Association for Computing Machinery (ACM)