//  file :s349.v
//# 9 inputs 
//# 11 outputs 
//# 15 D-type flipflops 
//# 57 inverters 
//# 104 gates (44 ANDs + 19 NANDs + 10 ORs + 31 NORs) 
 
 
module s349(GND,VDD,CK,A0,A1,A2,A3,B0,B1,B2,B3,CNTVCO2,CNTVCON2,P0,P1,P2,P3,P4, 
P5,P6,P7,READY,START); 
input GND,VDD,CK,START,B0,B1,B2,B3,A0,A1,A2,A3; 
output CNTVCO2,CNTVCON2,READY,P0,P1,P2,P3,P4,P5,P6,P7; 
 
wire CT2,CNTVG3VD,CT1,CNTVG2VD,CT0,CNTVG1VD,ACVQN3,ACVG4VD1,ACVQN2,ACVG3VD1, 
ACVQN1,ACVG2VD1,ACVQN0,ACVG1VD1,MRVQN3,MRVG4VD,MRVQN2,MRVG3VD,MRVQN1, 
MRVG2VD,MRVQN0,MRVG1VD,AX3,AM3,AX2,AM2,AX1,AM1,AX0,AM0,READYN,CT1N, 
CNTVG3VQN,CNTVG2VQN,CNTVCO0,CNTVG1VQN,CNTVCON0,CNTVG1VD1,S3,ADDVG4VSN,CO, 
ADDVG4VCN,S2,ADDVG3VSN,ADDVC3,ADDVG3VCN,S1,ADDVG2VSN,ADDVC2,ADDVG2VCN, 
ADDVC1,ADDVG1VCN,S0,ADDVG1VP,AD0,AD0N,AD1,AD1N,AD2,AD2N,AD3,AD3N,ACVPCN, 
SMVG5VS0P,SMVS0N,SM3,SMVG5VX,SMVG4VS0P,SM2,SMVG4VX,SMVG3VS0P,SM1,SMVG3VX, 
SMVG2VS0P,SM0,SMVG2VX,ADSH,MRVSHLDN,BMVG5VS0P,BMVS0N,BM3,BMVG5VX,BMVG4VS0P, 
BM2,BMVG4VX,BMVG3VS0P,BM1,BMVG3VX,BMVG2VS0P,BM0,BMVG2VX,AMVG5VS0P,AMVS0N, 
AMVG5VX,AMVG4VS0P,AMVG4VX,AMVG3VS0P,AMVG3VX,AMVG2VS0P,AMVG2VX,IINIIT, 
ADDVG4VCNVAD4NF,ADDVG4VCNVAD3NF,ADDVG4VCNVOR2NF,ADDVG4VCNVAD2NF, 
ADDVG4VCNVOR1NF,ADDVG4VCNVAD1NF,ADDVG3VCNVAD4NF,ADDVG3VCNVAD3NF, 
ADDVG3VCNVOR2NF,ADDVG3VCNVAD2NF,ADDVG3VCNVOR1NF,ADDVG3VCNVAD1NF, 
ADDVG2VCNVAD4NF,ADDVG2VCNVAD3NF,ADDVG2VCNVOR2NF,ADDVG2VCNVAD2NF, 
ADDVG2VCNVOR1NF,ADDVG2VCNVAD1NF,SMVG5VG1VAD2NF,SMVG5VG1VAD1NF, 
SMVG4VG1VAD2NF,SMVG4VG1VAD1NF,SMVG3VG1VAD2NF,SMVG3VG1VAD1NF,SMVG2VG1VAD2NF, 
SMVG2VG1VAD1NF,MRVG4VDVAD2NF,MRVG4VDVAD1NF,MRVG3VDVAD2NF,MRVG3VDVAD1NF, 
MRVG2VDVAD2NF,MRVG2VDVAD1NF,MRVG1VDVAD2NF,MRVG1VDVAD1NF,BMVG5VG1VAD2NF, 
BMVG5VG1VAD1NF,BMVG4VG1VAD2NF,BMVG4VG1VAD1NF,BMVG3VG1VAD2NF,BMVG3VG1VAD1NF, 
BMVG2VG1VAD2NF,BMVG2VG1VAD1NF,AMVG5VG1VAD2NF,AMVG5VG1VAD1NF,AMVG4VG1VAD2NF, 
AMVG4VG1VAD1NF,AMVG3VG1VAD2NF,AMVG3VG1VAD1NF,AMVG2VG1VAD2NF,AMVG2VG1VAD1NF, 
CNTVG3VG2VOR1NF,CNTVG3VD1,CNTVG2VG2VOR1NF,CNTVG2VD1,CNTVG1VG2VOR1NF, 
ADDVG1VPVOR1NF,CNTVCO1,CNTVG3VZ,CNTVG3VZ1,CNTVCON1,CNTVG2VZ,CNTVG2VZ1, 
CNTVG1VZ,CNTVG1VZ1; 
  DFA DFF_0 (  .C(CK), .Q(CT2), .D(CNTVG3VD) ); //, .RN(INIT), .SE(MODE), .SD(z__SI) ); 
  DFA DFF_1 (  .C(CK), .Q(CT1), .D(CNTVG2VD) ); //, .RN(INIT), .SE(MODE), .SD(CT2) ); 
  DFA DFF_2 (  .C(CK), .Q(CT0), .D(CNTVG1VD) ); //, .RN(INIT), .SE(MODE), .SD(CT1) ); 
  DFA DFF_3 (  .C(CK), .Q(ACVQN3), .D(ACVG4VD1) ); //, .RN(INIT), .SE(MODE), .SD(CT0) ); 
  DFA DFF_4 (  .C(CK), .Q(ACVQN2), .D(ACVG3VD1) ); //, .RN(INIT), .SE(MODE), .SD(ACVQN3) ); 
  DFA DFF_5 (  .C(CK), .Q(ACVQN1), .D(ACVG2VD1) ); //, .RN(INIT), .SE(MODE), .SD(ACVQN2) ); 
  DFA DFF_6 (  .C(CK), .Q(ACVQN0), .D(ACVG1VD1) ); //, .RN(INIT), .SE(MODE), .SD(ACVQN1) ); 
  DFA DFF_7 (  .C(CK), .Q(MRVQN3), .D(MRVG4VD) ); //, .RN(INIT), .SE(MODE), .SD(ACVQN0) ); 
  DFA DFF_8 (  .C(CK), .Q(MRVQN2), .D(MRVG3VD) ); //, .RN(INIT), .SE(MODE), .SD(MRVQN3) ); 
  DFA DFF_9 (  .C(CK), .Q(MRVQN1), .D(MRVG2VD) ); //, .RN(INIT), .SE(MODE), .SD(MRVQN2) ); 
  DFA DFF_10 (  .C(CK), .Q(MRVQN0), .D(MRVG1VD) ); //, .RN(INIT), .SE(MODE), .SD(MRVQN1) ); 
  DFA DFF_11 (  .C(CK), .Q(AX3), .D(AM3) ); //, .RN(INIT), .SE(MODE), .SD(MRVQN0) ); 
  DFA DFF_12 (  .C(CK), .Q(AX2), .D(AM2) ); //, .RN(INIT), .SE(MODE), .SD(AX3) ); 
  DFA DFF_13 (  .C(CK), .Q(AX1), .D(AM1) ); //, .RN(INIT), .SE(MODE), .SD(AX2) ); 
  DFA DFF_14 (  .C(CK), .Q(AX0), .D(AM0) ); //, .RN(INIT), .SE(MODE), .SD(AX1) ); 
  IN1 NOT_0 (  .Q(READY), .A(READYN) ); 
  IN1 NOT_1 (  .Q(CT1N), .A(CT1) ); 
  IN1 NOT_2 (  .Q(CNTVG3VQN), .A(CT2) ); 
  IN1 NOT_3 (  .Q(CNTVG2VQN), .A(CT1) ); 
  IN1 NOT_4 (  .Q(CNTVCO0), .A(CNTVG1VQN) ); 
  IN1 NOT_5 (  .Q(CNTVCON0), .A(CT0) ); 
  IN1 NOT_6 (  .Q(CNTVG1VQN), .A(CT0) ); 
  IN1 NOT_7 (  .Q(CNTVG1VD1), .A(READY) ); 
  IN1 NOT_8 (  .Q(S3), .A(ADDVG4VSN) ); 
  IN1 NOT_9 (  .Q(CO), .A(ADDVG4VCN) ); 
  IN1 NOT_10 (  .Q(S2), .A(ADDVG3VSN) ); 
  IN1 NOT_11 (  .Q(ADDVC3), .A(ADDVG3VCN) ); 
  IN1 NOT_12 (  .Q(S1), .A(ADDVG2VSN) ); 
  IN1 NOT_13 (  .Q(ADDVC2), .A(ADDVG2VCN) ); 
  IN1 NOT_14 (  .Q(ADDVC1), .A(ADDVG1VCN) ); 
  IN1 NOT_15 (  .Q(S0), .A(ADDVG1VP) ); 
  IN1 NOT_16 (  .Q(AD0), .A(AD0N) ); 
  IN1 NOT_17 (  .Q(AD1), .A(AD1N) ); 
  IN1 NOT_18 (  .Q(AD2), .A(AD2N) ); 
  IN1 NOT_19 (  .Q(AD3), .A(AD3N) ); 
  IN1 NOT_20 (  .Q(ACVPCN), .A(START) ); 
  IN1 NOT_21 (  .Q(P7), .A(ACVQN3) ); 
  IN1 NOT_22 (  .Q(P6), .A(ACVQN2) ); 
  IN1 NOT_23 (  .Q(P5), .A(ACVQN1) ); 
  IN1 NOT_24 (  .Q(P4), .A(ACVQN0) ); 
  IN1 NOT_25 (  .Q(SMVG5VS0P), .A(SMVS0N) ); 
  IN1 NOT_26 (  .Q(SM3), .A(SMVG5VX) ); 
  IN1 NOT_27 (  .Q(SMVG4VS0P), .A(SMVS0N) ); 
  IN1 NOT_28 (  .Q(SM2), .A(SMVG4VX) ); 
  IN1 NOT_29 (  .Q(SMVG3VS0P), .A(SMVS0N) ); 
  IN1 NOT_30 (  .Q(SM1), .A(SMVG3VX) ); 
  IN1 NOT_31 (  .Q(SMVG2VS0P), .A(SMVS0N) ); 
  IN1 NOT_32 (  .Q(SM0), .A(SMVG2VX) ); 
  IN1 NOT_33 (  .Q(SMVS0N), .A(ADSH) ); 
  IN1 NOT_34 (  .Q(MRVSHLDN), .A(ADSH) ); 
  IN1 NOT_35 (  .Q(P3), .A(MRVQN3) ); 
  IN1 NOT_36 (  .Q(P2), .A(MRVQN2) ); 
  IN1 NOT_37 (  .Q(P1), .A(MRVQN1) ); 
  IN1 NOT_38 (  .Q(P0), .A(MRVQN0) ); 
  IN1 NOT_39 (  .Q(BMVG5VS0P), .A(BMVS0N) ); 
  IN1 NOT_40 (  .Q(BM3), .A(BMVG5VX) ); 
  IN1 NOT_41 (  .Q(BMVG4VS0P), .A(BMVS0N) ); 
  IN1 NOT_42 (  .Q(BM2), .A(BMVG4VX) ); 
  IN1 NOT_43 (  .Q(BMVG3VS0P), .A(BMVS0N) ); 
  IN1 NOT_44 (  .Q(BM1), .A(BMVG3VX) ); 
  IN1 NOT_45 (  .Q(BMVG2VS0P), .A(BMVS0N) ); 
  IN1 NOT_46 (  .Q(BM0), .A(BMVG2VX) ); 
  IN1 NOT_47 (  .Q(BMVS0N), .A(READYN) ); 
  IN1 NOT_48 (  .Q(AMVG5VS0P), .A(AMVS0N) ); 
  IN1 NOT_49 (  .Q(AM3), .A(AMVG5VX) ); 
  IN1 NOT_50 (  .Q(AMVG4VS0P), .A(AMVS0N) ); 
  IN1 NOT_51 (  .Q(AM2), .A(AMVG4VX) ); 
  IN1 NOT_52 (  .Q(AMVG3VS0P), .A(AMVS0N) ); 
  IN1 NOT_53 (  .Q(AM1), .A(AMVG3VX) ); 
  IN1 NOT_54 (  .Q(AMVG2VS0P), .A(AMVS0N) ); 
  IN1 NOT_55 (  .Q(AM0), .A(AMVG2VX) ); 
  IN1 NOT_56 (  .Q(AMVS0N), .A(IINIIT) ); 
  AND3 AND3_0 (  .Q(ADDVG4VCNV), .A(ADDVC3), .B(AD3), .C(P7) ); 
  AND2 AND2_0 (  .Q(ADDVG4VCNV), .A(ADDVG4VCNV), .B(ADDVG4VCN) ); 
  AND2 AND2_1 (  .Q(ADDVG4VCNV), .A(ADDVC3), .B(ADDVG4VCNV) ); 
  AND2 AND2_2 (  .Q(ADDVG4VCNV), .A(AD3), .B(P7) ); 
  AND3 AND3_1 (  .Q(ADDVG3VCNV), .A(ADDVC2), .B(AD2), .C(P6) ); 
  AND2 AND2_3 (  .Q(ADDVG3VCNV), .A(ADDVG3VCNV), .B(ADDVG3VCN) ); 
  AND2 AND2_4 (  .Q(ADDVG3VCNV), .A(ADDVC2), .B(ADDVG3VCNV) ); 
  AND2 AND2_5 (  .Q(ADDVG3VCNV), .A(AD2), .B(P6) ); 
  AND3 AND3_2 (  .Q(ADDVG2VCNV), .A(ADDVC1), .B(AD1), .C(P5) ); 
  AND2 AND2_6 (  .Q(ADDVG2VCNV), .A(ADDVG2VCNV), .B(ADDVG2VCN) ); 
  AND2 AND2_7 (  .Q(ADDVG2VCNV), .A(ADDVC1), .B(ADDVG2VCNV) ); 
  AND2 AND2_8 (  .Q(ADDVG2VCNV), .A(AD1), .B(P5) ); 
  AND2 AND2_9 (  .Q(SMVG5VG1VA), .A(SMVG5VS0P), .B(CO) ); 
  AND2 AND2_10 (  .Q(SMVG5VG1VA), .A(SMVS0N), .B(P7) ); 
  AND2 AND2_11 (  .Q(SMVG4VG1VA), .A(SMVG4VS0P), .B(S3) ); 
  AND2 AND2_12 (  .Q(SMVG4VG1VA), .A(SMVS0N), .B(P6) ); 
  AND2 AND2_13 (  .Q(SMVG3VG1VA), .A(SMVG3VS0P), .B(S2) ); 
  AND2 AND2_14 (  .Q(SMVG3VG1VA), .A(SMVS0N), .B(P5) ); 
  AND2 AND2_15 (  .Q(SMVG2VG1VA), .A(SMVG2VS0P), .B(S1) ); 
  AND2 AND2_16 (  .Q(SMVG2VG1VA), .A(SMVS0N), .B(P4) ); 
  AND2 AND2_17 (  .Q(MRVG4VDVAD), .A(MRVSHLDN), .B(BM3) ); 
  AND2 AND2_18 (  .Q(MRVG4VDVAD), .A(ADSH), .B(S0) ); 
  AND2 AND2_19 (  .Q(MRVG3VDVAD), .A(MRVSHLDN), .B(BM2) ); 
  AND2 AND2_20 (  .Q(MRVG3VDVAD), .A(ADSH), .B(P3) ); 
  AND2 AND2_21 (  .Q(MRVG2VDVAD), .A(MRVSHLDN), .B(BM1) ); 
  AND2 AND2_22 (  .Q(MRVG2VDVAD), .A(ADSH), .B(P2) ); 
  AND2 AND2_23 (  .Q(MRVG1VDVAD), .A(MRVSHLDN), .B(BM0) ); 
  AND2 AND2_24 (  .Q(MRVG1VDVAD), .A(ADSH), .B(P1) ); 
  AND2 AND2_25 (  .Q(BMVG5VG1VA), .A(BMVG5VS0P), .B(B3) ); 
  AND2 AND2_26 (  .Q(BMVG5VG1VA), .A(BMVS0N), .B(P3) ); 
  AND2 AND2_27 (  .Q(BMVG4VG1VA), .A(BMVG4VS0P), .B(B2) ); 
  AND2 AND2_28 (  .Q(BMVG4VG1VA), .A(BMVS0N), .B(P2) ); 
  AND2 AND2_29 (  .Q(BMVG3VG1VA), .A(BMVG3VS0P), .B(B1) ); 
  AND2 AND2_30 (  .Q(BMVG3VG1VA), .A(BMVS0N), .B(P1) ); 
  AND2 AND2_31 (  .Q(BMVG2VG1VA), .A(BMVG2VS0P), .B(B0) ); 
  AND2 AND2_32 (  .Q(BMVG2VG1VA), .A(BMVS0N), .B(P0) ); 
  AND2 AND2_33 (  .Q(AMVG5VG1VA), .A(AMVG5VS0P), .B(A3) ); 
  AND2 AND2_34 (  .Q(AMVG5VG1VA), .A(AMVS0N), .B(AX3) ); 
  AND2 AND2_35 (  .Q(AMVG4VG1VA), .A(AMVG4VS0P), .B(A2) ); 
  AND2 AND2_36 (  .Q(AMVG4VG1VA), .A(AMVS0N), .B(AX2) ); 
  AND2 AND2_37 (  .Q(AMVG3VG1VA), .A(AMVG3VS0P), .B(A1) ); 
  AND2 AND2_38 (  .Q(AMVG3VG1VA), .A(AMVS0N), .B(AX1) ); 
  AND2 AND2_39 (  .Q(AMVG2VG1VA), .A(AMVG2VS0P), .B(A0) ); 
  AND2 AND2_40 (  .Q(AMVG2VG1VA), .A(AMVS0N), .B(AX0) ); 
  OR2 OR2_0 (  .Q(CNTVG3VG2V), .A(CT2), .B(CNTVG3VD1) ); 
  OR2 OR2_1 (  .Q(CNTVG2VG2V), .A(CT1), .B(CNTVG2VD1) ); 
  OR2 OR2_2 (  .Q(CNTVG1VG2V), .A(CT0), .B(CNTVG1VD1) ); 
  OR3 OR3_0 (  .Q(ADDVG4VCNV), .A(ADDVC3), .B(AD3), .C(P7) ); 
  OR2 OR2_3 (  .Q(ADDVG4VCNV), .A(AD3), .B(P7) ); 
  OR3 OR3_1 (  .Q(ADDVG3VCNV), .A(ADDVC2), .B(AD2), .C(P6) ); 
  OR2 OR2_4 (  .Q(ADDVG3VCNV), .A(AD2), .B(P6) ); 
  OR3 OR3_2 (  .Q(ADDVG2VCNV), .A(ADDVC1), .B(AD1), .C(P5) ); 
  OR2 OR2_5 (  .Q(ADDVG2VCNV), .A(AD1), .B(P5) ); 
  OR2 OR2_6 (  .Q(ADDVG1VPVO), .A(AD0), .B(P4) ); 
  NA3 NAND3_0 (  .Q(READYN), .A(CT0), .B(CT1N), .C(CT2) ); 
  NA2 NAND2_0 (  .Q(CNTVCON2), .A(CT2), .B(CNTVCO1) ); 
  NA2 NAND2_1 (  .Q(CNTVG3VZ), .A(CNTVG3VG2V), .B(CNTVG3VZ1) ); 
  NA2 NAND2_2 (  .Q(CNTVG3VZ1), .A(CT2), .B(CNTVG3VD1) ); 
  NA2 NAND2_3 (  .Q(CNTVCON1), .A(CT1), .B(CNTVCO0) ); 
  NA2 NAND2_4 (  .Q(CNTVG2VZ), .A(CNTVG2VG2V), .B(CNTVG2VZ1) ); 
  NA2 NAND2_5 (  .Q(CNTVG2VZ1), .A(CT1), .B(CNTVG2VD1) ); 
  NA2 NAND2_6 (  .Q(CNTVG1VZ), .A(CNTVG1VG2V), .B(CNTVG1VZ1) ); 
  NA2 NAND2_7 (  .Q(CNTVG1VZ1), .A(CT0), .B(CNTVG1VD1) ); 
  NA2 NAND2_8 (  .Q(ADDVG1VP), .A(ADDVG1VPVO), .B(ADDVG1VCN) ); 
  NA2 NAND2_9 (  .Q(ADDVG1VCN), .A(AD0), .B(P4) ); 
  NA2 NAND2_10 (  .Q(AD0N), .A(P0), .B(AX0) ); 
  NA2 NAND2_11 (  .Q(AD1N), .A(P0), .B(AX1) ); 
  NA2 NAND2_12 (  .Q(AD2N), .A(P0), .B(AX2) ); 
  NA2 NAND2_13 (  .Q(AD3N), .A(P0), .B(AX3) ); 
  NA2 NAND2_14 (  .Q(ACVG4VD1), .A(ACVPCN), .B(SM3) ); 
  NA2 NAND2_15 (  .Q(ACVG3VD1), .A(ACVPCN), .B(SM2) ); 
  NA2 NAND2_16 (  .Q(ACVG2VD1), .A(ACVPCN), .B(SM1) ); 
  NA2 NAND2_17 (  .Q(ACVG1VD1), .A(ACVPCN), .B(SM0) ); 
  NO2 NOR2_0 (  .Q(ADSH), .A(READY), .B(IINIIT) ); 
  NO3 NOR3_0 (  .Q(IINIIT), .A(CT0), .B(CT1), .C(CT2) ); 
  NO2 NOR2_1 (  .Q(CNTVCO2), .A(CNTVG3VQN), .B(CNTVCON1) ); 
  NO2 NOR2_2 (  .Q(CNTVG3VD), .A(CNTVG3VZ), .B(START) ); 
  NO2 NOR2_3 (  .Q(CNTVG3VD1), .A(READY), .B(CNTVCON1) ); 
  NO2 NOR2_4 (  .Q(CNTVCO1), .A(CNTVG2VQN), .B(CNTVCON0) ); 
  NO2 NOR2_5 (  .Q(CNTVG2VD), .A(CNTVG2VZ), .B(START) ); 
  NO2 NOR2_6 (  .Q(CNTVG2VD1), .A(READY), .B(CNTVCON0) ); 
  NO2 NOR2_7 (  .Q(CNTVG1VD), .A(CNTVG1VZ), .B(START) ); 
  NO2 NOR2_8 (  .Q(ADDVG4VSN), .A(ADDVG4VCNV), .B(ADDVG4VCNV) ); 
  NO2 NOR2_9 (  .Q(ADDVG4VCN), .A(ADDVG4VCNV), .B(ADDVG4VCNV) ); 
  NO2 NOR2_10 (  .Q(ADDVG3VSN), .A(ADDVG3VCNV), .B(ADDVG3VCNV) ); 
  NO2 NOR2_11 (  .Q(ADDVG3VCN), .A(ADDVG3VCNV), .B(ADDVG3VCNV) ); 
  NO2 NOR2_12 (  .Q(ADDVG2VSN), .A(ADDVG2VCNV), .B(ADDVG2VCNV) ); 
  NO2 NOR2_13 (  .Q(ADDVG2VCN), .A(ADDVG2VCNV), .B(ADDVG2VCNV) ); 
  NO2 NOR2_14 (  .Q(SMVG5VX), .A(SMVG5VG1VA), .B(SMVG5VG1VA) ); 
  NO2 NOR2_15 (  .Q(SMVG4VX), .A(SMVG4VG1VA), .B(SMVG4VG1VA) ); 
  NO2 NOR2_16 (  .Q(SMVG3VX), .A(SMVG3VG1VA), .B(SMVG3VG1VA) ); 
  NO2 NOR2_17 (  .Q(SMVG2VX), .A(SMVG2VG1VA), .B(SMVG2VG1VA) ); 
  NO2 NOR2_18 (  .Q(MRVG4VD), .A(MRVG4VDVAD), .B(MRVG4VDVAD) ); 
  NO2 NOR2_19 (  .Q(MRVG3VD), .A(MRVG3VDVAD), .B(MRVG3VDVAD) ); 
  NO2 NOR2_20 (  .Q(MRVG2VD), .A(MRVG2VDVAD), .B(MRVG2VDVAD) ); 
  NO2 NOR2_21 (  .Q(MRVG1VD), .A(MRVG1VDVAD), .B(MRVG1VDVAD) ); 
  NO2 NOR2_22 (  .Q(BMVG5VX), .A(BMVG5VG1VA), .B(BMVG5VG1VA) ); 
  NO2 NOR2_23 (  .Q(BMVG4VX), .A(BMVG4VG1VA), .B(BMVG4VG1VA) ); 
  NO2 NOR2_24 (  .Q(BMVG3VX), .A(BMVG3VG1VA), .B(BMVG3VG1VA) ); 
  NO2 NOR2_25 (  .Q(BMVG2VX), .A(BMVG2VG1VA), .B(BMVG2VG1VA) ); 
  NO2 NOR2_26 (  .Q(AMVG5VX), .A(AMVG5VG1VA), .B(AMVG5VG1VA) ); 
  NO2 NOR2_27 (  .Q(AMVG4VX), .A(AMVG4VG1VA), .B(AMVG4VG1VA) ); 
  NO2 NOR2_28 (  .Q(AMVG3VX), .A(AMVG3VG1VA), .B(AMVG3VG1VA) ); 
  NO2 NOR2_29 (  .Q(AMVG2VX), .A(AMVG2VG1VA), .B(AMVG2VG1VA) ); 
endmodule