CURRICULUM VITAE

Personal data:
 

Name:

 Raimund-Johannes Ubar

Academic titles: 

 Professor, Dr.sc.techn.

Position:

 Head of the Chair for Computer Engineering and Diagnostics,
 Tallinn Technical University

Address:

 Raja tee 15,
 Tallinn, 12618, Estonia
 Tel.:  (372) 620 2252
 Fax:  (372) 620 2253
 E-mail: raiub@pld.ttu.ee

1. EDUCATIONAL INFORMATION

1986 - Doctor of Engineering Science (Dr.sc.),  Computer Engineering, Institut of Electronics and Computer Engineering in Riga, Latvia
1971 - Doctor of Philosophy (PhD), Electrical Engineering, Bauman Technical University of Moscow, Russia
1965 - Diploma of Engineer (MS), Control Engineering, Tallinn Technical University, Estonia

2. INDUSTRIAL CAREER

1965 - 1968  Engineer, Group leader at the R&D Laboratory of Electronics at the Plant  "Punane Ret" in Tallinn (Estonia)

3. ACADEMIC CAREER AT THE TALLINN TECHNICAL UNIVERSITY

1997 -  Professor, Head of the Chair of Computer Engineering and Diagnostics,
1993 - 97 Professor, Head of the Electronics Competence Center
1987 - 92 Professor, Head of the Department of Computer Engineering
1978 - 87 Associate professor
1971 - 78  Senior lecturer
1971    Assistant

4. ACADEMIC ACTIVITIES IN OTHER COUNTRIES

Longer stays:

2001 - 05 Visiting professor, Jönköping University (Sweden) 2 months per year
2000 Linköping University (Sweden) 3 months

1999 Joseph Fourier University Grenoble (France) 2 months

1998 TIMA Laboratory Grenoble (France) 2 months

1998  Joseph Fourier University Grenoble (France) 4 months
1997  Fraunhofer Institute of Integrated Circuits, Dresden (Germany) 3 months
1996  Politechnico di Torino (Italy) 2 months
1996  Michigan State University, Virginia Tech (USA) 1 month
1995  Grenoble National Polytechn. Institute (France) 1,5 months
1994  Grenoble National Polytechn. Institute (France) 2 months
1993  Darmstadt Technical University (Germany) 1 month
1992  Grenoble National Polytechnical Inst. (France) 4 months
1991  University of Linköping (Sweden) 2 months
1990  University of Linköping (Sweden) 1 month
1988  Visiting professor Technical University Dresden (Germany) 4 months
           Barkhausen International Chair
1983  Visiting Ass. Professor, Ingenieurhochschule Wismar (Germany) 3 months
1975 - 76  Technical University Dresden (Germany) 10 months

Lecture courses or seminars:

in about 25 universities and institutes  in  Germany, France, Italy, Sweden, Norway, Finland, Denmark, Hungary, Poland, USA, Russland, Lettland a.o..

2002 - 06 TU Darmstadt (Germany) 16 h per year

2003 - 05 About 20 tutorials in 10 countries (Europe)

2001  Linköping University, Jönköping Umiversity (Sweden)

2000  Linköping University (Sweden)

1998  Ericsson Telecom AB Stockholm (Sweden)
1998  Joseph Fourier University Grenoble (France)
1998, 1992 Technical University of Dresden (Germany)
1998, 1994 Fraunhofer Assotiation in Dresden (Germany)
1997   Brandenburg Technical University in Cottbus (Germany)
1996   Politechnico di Torino, University Pisa (Italy)
            Michigan State University, Virginia Tech (USA)  
1995   Technical University of Helsinki (Finland) 16 h
1994,  1993 Technical University of Darmstadt (Germany) 12 h
1993,  1990 Royal Institute of Technology in Stockholm (Sweden)
1993   Technical University Lyngby (Denmark)
1991,  1990 Linköping University (Sweden) 16 h
1989   TU Riga (Latvia) 32 h
             TU Warsaw (Poland)
             KTH iStockholm, TU Chalmers, Linköping U (Sweden)
             TU Ilmenau 14 h, Ingenieurhochschule Berlin (Germany)
1988   TU Ilmenau 10 h, TU Dresden 16 h, TU Chemnitz (Germany) 12 h
             University Leipzig, Institute of Cybernetics, Dresden (Germany)
1987    Technical University of Budapest (Hungary)
1987, 1986 TU Ilmenau (Germany) 10 h
1986    University LITMO, St.-Peterburg (Russia)
             Institut of Simulation in Power Engineering, Kiew (Ukraine)
             Institut of Electronics and Computer Engineering, Riga (Latvia)
1984    IHS Wismar (Germany) 8 h
             Institut für Kübernetik, Dresden (Germany)
1983    TU Ilmenau (Germany) 12 h
1980, 1977 His Dresden (Germany)
1980    TU Ilmenau (Germany) 12 h
             Institut of Control Engineering, Vladivostok, Russia
1978    Institut of Control Engineering (IAT), Moscow, Russia
1977, 1976 TU Ilmenau (Germany) 12 h

5. PEDAGOGICAL WORK

Main lecture courses held:

Switching Theory, Digital Electronics, Theory and Design of Computers, Digital Test and Fault Diagnosis, Design for Testability, Fault-Tolerant Computing

Experience:

Computer Science, Applied Mathematics, Electrical Engineering, Computer Engineering, Switching Theory, Digital Test and Fault Diagnosis, Design for Testability, Fault-Tolerant Computing, Intelligent Digital Test Systems

Supervising (40 defenced degrees):

·         PhD thesis (11): E.Orasson (2007), E.Ivask (2006), A.Jutman (2004), M.Brik (2002), J.Raik (2001), J.Dushina (1999), T.Evartson (1987), A.Voolaine (1986), M.Pall (1986), M.Plakk (1984), P.Kitsnik (1981)

·         MSc thesis (29): S.Kostin (2007), A.Kurbatov, J.Sudbrock, T.Schchenova (2005), D.Zhukov, J.Grüning, J.Tünni, M.Jenihhin, V.Govind, J.Smahtina, N.Mazurova, V.Vislogubov (2004), H.Kruus (2003), E.Orasson, R.Raidma (2002), M.Aarna, J.Heinlaid, L.Raun (2001), A.Jutman (1999), G.Jervan, E.Ivask, P.Paomets (1998), J.Raik (1997), M.Brik (1994), A.Buldas, H.Krupnova, S.Storozhev, J.Dushina, V.Zaugarov (1993)

6. RESEARCH WORK

Current research activities:

1.      Decision Diagrams and Diagnostic Modeling of Digital Systems

2.      Test Synthesis and Analysis for Digital Circuits and Systems

3.      Fault Diagnosis in Digital Circuits and Systems

4.      Self-Testing Digital Systems

5.      Development of CAD Tools for Digital Test Design

European projects:

1.      V Framework IST 033709 Verification and validation of Embedded System Design workbench – VERTIGO (2006 -2008)

2.      V Framework IST-2001-37592 Establishment of the Virtual Centre of  Excellence for IST RTD in Estonia -eVIKINGS II (2002 - 2005)

3.      V Framework IST-2000-30193 Research and Training Actionfor System on Chip Design - REASON (2002 - 2005)

4.      European Thematic Network 10063-CP-1-2000-1-PT-ERASMUS-ETNE Thematic Harmonisation in Electrical and Information EngineeRing in Europe – THEIERE (2002-2005)

5.      INCO JEP 977133 Microelectronics Virtual Laboratory for Cooperation in Research and Knowledge Transfer - VILAB (1998-2001)

6.      INCO-COPERNICUS JEP 9601/70 Promotion of System Design Training and Information Centers in CCE/NIS - SYTIC (1996-1998)

7.      COPERNICUS JEP 9624 Functional Test Generation  and  Diagnosis – FUTEG (1994-1997)

8.      PECO JEP 7668 East European Microelectronics Cooperation Network of Support and Competence Centres - EEMCN (1993-1996)

9.      ESPRIT III BRA-6575 Advanced test generation and testable design methodology for sequential circuits - ATSEC (1994-1996)

10.  ESPRIT Action EUROPRACTICE (1995 -)

11.  ESPRIT Action EUROCHIP (1993-1995)

12. Promotion of the use of professional CAD  software at universities EUROCHIP Action (1993 - 1995)

13.  TEMPUS JEP 4772 "Digital System Design Based on PLD-Technology" (1992-95)

Bilateral international projects:

1.      Estonian - Polish Joint Research Project. Analysis and Testing of Physical Defects in Digital Circuits and Systems. Partner: TU Warsaw (2007-2009)

2.      German-Estonian project. MOSCITO-based Test Tool Integration for Resarch and eLearning aided Education. Partner: Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden (2004-2006)

3.      Estonian- Polish Joint Research Project. Defect-Oriented Testing of  Digital Systems. Partner: TU Warsaw (2003-2005)

4.      German-Estonian project DILDIS. Distance Learning on Digital Systems. Partner: TU Ilmenau (2002-2006)

5.      German-Estonian project. Functional Built-in Self-Test in Digital Systems. Partners: Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden; University Stuttgart (2000-2002).

6.      German-Estonian project DILDIS. Distance Learning on Digital Systems. Partner: TU Ilmenau (1999-2001).

7.      Swedish-Estonian project. Design and Test of Dependable Electronic Systems. Partner: Linköping University (1999-2000).

8.      German-Estonian project. EST-008-96 Automated Test Generation for FPGA based Designs. Partner: Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden (1996-1999).

9.      Estonian - Swedish project. Generic VHDL Descriptions for Synthesizing Embedded Test Processors. Partner: Jonköping University (1996-1997).

10.  Digital Encryption Standard Macroblock. Partner: Fincitec OY Finland (1996).

National grants and projects:

1.      Excellence Centre of Dependable Computing (2003-2007).

2.      Target financing: Design and Test of Digital Systems (2003-2007).

3.      Estonian Academy of Sciences: Research Professor  on Digital Testing (2003-2005).

4.      Target financing: R6D and Applications of Design and Test of Digital Systems (1998-2002).

5.      Basic financing: Environment for Modeling of Self Test in Digital Systems (2007)

6.      Basic financing:: Cofinancing for EU Project VERTIGO (2006).

7.      Estonian Science Foundation Grant 5910. Self-Testing Digital Systems (2004-2007)

8.      ETS Grant 5649. Defect-Oriented Test of Digital Systems (2003-2006).

9.      ETS Grant 4003. Design Error Diagnosis of Digital Systems (200-2003).

10.  ETS Grant 3658. Virtual Laboratory of Design and Test (1999-2002).

11.  ETS Grant 1850. Investigation of Hierarchical Methods for Diagnostic Analysis of Digital Systems (1996-1999).

12.  ETS Grant 2104. Research Environment for Research and Design of Digital Electronics (1996-1998).

13.  ETS Grant 1434. Infrastructure of the Electronics Competence Centre (1993).

14.  ETS Grant 1433. Methods and Software of  Digital Test (1993-1995).

15.  Information Foundation Grant (Contract No. 227). Environment for Design of Data Security Hardware  (1993-1995).

16.  Innovation Foundation Grant. Design of  Electronics and Computing Systems (1994-1995).

17.  National Grant for the Electronics Competence Centre at TTU (1994-1995).

Contracts with Industry

1.      Contract: Conception and Diagnostic Means for Microprocessor Self Test – MIKROTEST. Partner: Artec Design (2001-2003).

2.      Contract: Testing of Cryptochip. Partner: Institute of Cybernetics (1996-1997).

3.      Contract No 6412: Design of the technological File of a Cryptochip. Partner: Institute of Cybernetics (1996).

Organizational activities (international level):

1.      IEEE  – Computer Society Golden Core Member (2006)

2.      Test Technology Technical Committee - TTTC, member (1998 -)

3.      European Test Technology Technical Committee - ETTTC, member (1995 -)

4.      Nordic Test Forum, member (2005 -)

5.      Council of the European Assotiation of Electrical and Information Engineers - EAEEIE, member (2001- )

6.      International Academy of Sciences and Arts (USA) , member (1996 -)

7.      Baltic Academy of Technological Sciences (founder member, 1992 -)

8.      Nordic and Baltic Journal of Information and Communication Technologies, Advisory Board – member (2006 -)

9.      Journal of Information Technology and Control, Editorial board (2005 -)

10.  IEEE Education Society, member (1995 -)

11.  IEEE Circuits and Systems Society, member (1995 -)

12.  IEEE Technical Council on Software Engineering European regional group (1995 -)

13.  IEEE Computer Society, member (1994 -)

14.  Institution of Engineering and Technology (previous IEE), member (2005 -)

15. Assotiation for Computin Mashinery, member (1996 -)

16. German Information Society – GI, member (1995 -)

17. Assotiation EUROPRACTICE, member (1995 -)

18. Assotiation EUROCHIP, member (1993-1995)

19. 10th IEEE European Test Symposion – General Chair (2005)

20. IEEE Conference NORCHIP – General Chair (1997)

21. 9th IEEE European Test Symposion – General Vice Chair (2005)

22. IEEE East-West Design & Test Conferences EWDTW'03, EWDTW'04, EWDTW'05, EWDTW'06, EWDTS'07 – General Vice Chair (2003 -)

23. International Conference on Microelectronics, Devices and materials (MIDEM) - General Vice Chair (2007)

24. IEEE VLSI Test Symposion (VTS) - Eastern Europe Liaison (2007 -)

25. IEEE Latin American Test Workshop (LATW) - Eastern Europe Liaison (2007 -)

26. IEEE Workshop on Design and Diagnostics of Electronic System (DDECS) – Publicity Chair (2005 -)

27. Council of the All-Union Association of Technical Diagnostics (1991-1993)

28. Member of Steering Committees of Conferences: VTS, EDCC, DDECS, LATW, EWD&TS, NORCHIP, BEC

29.  Member of Program Committees of Conferences: DATE, ISQED, VTS, LATW, EDCC, ETW, ETS, EWDC, ECCTD, DSD, IMCL, DDECS, EUROMICRO, NORCHIP, IWoTA, MIXDES, ITHET, EAEEIE, MIDEM, ECS, AQTR, EWDTW, BEC a.o.

Organizational activities (national level):

1.      Estonian Academy of Sciences, member (1993 -)

2.      Academic Board at the Estonian President, member (1993-1996)

3.      Estonian Research and Development Council, member (1993-1997)

4.      Estonian Science Foundation, Chairman (1993-1997)

5.      ESF, Board of Experts for Technical Sciences, Chairman (1993-1997)

6.      EAS, Board of Experts on National Science Awards, member (1994-1996, 2004 -)

7.      EAS, Board of Division of Informatics and Engineering (1994 -)

8.      Estonian Union of  Scientists , Council, member (1991 - 2005)

9.      Estonian Society of Control Engineers, member (1991 -)

10.  Estonian Electronics Society, member (1992 -)

11.  Estonian Council of Informatics, expert (1993 -1996 )

12.  Estonian Higher Education Ministery,  Estonian-German Comission for Cooperation (1994 - 1997)

7. Awards

2006  IEEE Computer Society Golden Core Award

2005  IEEE Computer Society Meritorious Service Award

2003  Professor Honoris Causa of the Harkov National University of Radioelectronics

2002  Governmental award: White Cross Orden of III Class

2001  Meritorious Service Medal of the Tallinn University of Technology "Mente et Manu"

1999  National Science Prize on Natural Sciences and Engineering

1997  Gold Medal of Tallinn University of Technology
1986  2 Silber Medals from the Exhibition of the National Economy in Moscow

8. Selected Publications

Books

  1. O.Novak, E.Gramatova, R.Ubar. Handbook of Electronic Testing. CTU Printhouse, Prague, 2005, 400 p
  2. D.Bochmann, R.Ubar.  Fehler in Automaten. VEB  Verlag  Technik, Berlin, 1989,  216 p.
  3. A.Seleznev, B.Dobriza, R.Ubar. Design of Automatic Test Equipments. Mashinostrojenie,  Moscow, USSR, 1983, 224 p. (in Russian).

 

Patents in SU

  1. Equipment for testing  VLSI.  (T.Lohuaru,  M.Männisalu,  P.Pukk,  R.Ubar, E.Vanamölder). A.C. No. SU 1652976 A1, Inf. Bulletin No.20, 1991.
  2. Equipment for Fault Localization in Digital Objects. (T.Evartson, H.Haak, T.Lohuaru, R.Ubar), A.C. No.3984709/24, Inf. Bulletin No.19, 1987.
  3. Equipment for Testing LSI. (T. Lohuaru and R.Ubar), A.C. No.1218390, Inf. Bull. No.10   1986.
  4. Equipment  for  Testing  Synchronized  digital   circuits.  (T.Evartson, R.Ubar, A.Viilup), A.C. No.3772884/24, Inf. Bulletin No.25, 1986.

Selected papers (2003 - 2008)

2008

1.      R.Ubar, S.Devadze, J.Raik, A.Jutman. Fast Fault Simulation in Digital Circuits with Scan Path. 13th Asia and South Pacific Design Automation Conference – ASP-DAC 2008, Seoul, Korea, Jan. 21-24, 2008, (to appear).

2.      R.Ubar, S.Devadze, M.Jenihhin, J.Raik, G.Jervan, P.Ellervee. Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. 4th IEEE International Symposium on Electronic Design, Test & Applications – DELTA 2008, Hong Kong, January 23-25, 2008 (to appear).

2007

1.      J.Raik, R.Ubar, T.Viilukas, M.Jenihhin. Mixed Hierarchical-Functional Fault Models for Targeting Sequential Cores. Journal of Systems Architecture, 2007 (to appear).

2.      R.Ubar, J.Raik, H.Kruus, H.Lensen, T.Evartson. Diagnostic Modelling of Digital Systems with Binary and High-Level Decision Diagrams. In “Progress in Industrial Mathematics at ECMI 2006”, Series: Mathematics in Industry, Subseries: The European Consortium for Mathematics in Industry , Vol. 12, 2007.

3.      P.Ellervee, J.Raik, R.Ubar, K.Tammemäe. FPGA-Based Fault Emulation of Synchronous Sequential Circuits. IEE Proceedings on Computers & Digital Techniques. Vol.1, Issue 2, pp.70-76, March 2007.

4.      R.Ubar, A.Jutman, M.Kruus, E.Orasson, S.Devadze, H.-D.Wuttke. Learning Digital Test and Diagnostics via Internet. International Journal of Emerging Technologies in Learning. International Journal of Online Engineering, Vol.3, No.1, pp.1-9, 2007.

5.      R.Ubar, M.Kruus, T.Rang. Electronics Design and Test. Public Service Review: European Union, Issue 13, 2007, p.52-53.

6.      R.Ubar, S.Devadze, J.Raik, A.Jutman. Ultra Fast Parallel Fault Analysis on Structural BDDs. 12th IEEE European Test Symposium – ETS 2007, Freiburg, Germany, May 20-24, 2007, pp.131-136.

7.      G.Jervan, H.Kruus, E.Orasson, R.Ubar. Hybrid BIST Optimization Using Reseeding and Test Set Compaction. Proc. of 10th IEEE EUROMICRO Conference on Digital System Design - DSD 2007, Lübeck, Germany, August 27 - 31, 2007, pp.596-603.

8.      J.Raik, R.Ubar, A.Krivenko, M.Kruus. Hierarchical Identification of Untestable Faults in Sequential Circuits. Proc. of 10th IEEE EUROMICRO Conference on Digital System Design - DSD 2007, Lübeck, Germany, August 27 - 31, 2007, pp.668-671.

9.      R.Ubar, S.Kostin, J.Raik, T.Evartson, H.Lensen. Fault Diagnosis in Integrated Circuits with BIST. Proc. of 10th IEEE EUROMICRO Conference on Digital System Design - DSD 2007, Lübeck, Germany, August 27 - 31, 2007, pp.604-610.

10. M.Jenihhin, J.Raik, A.Chepurov, R.Ubar. Assertion Checking with PSL and High-Level Decision Diagrams. Diggest of Papers IEEE 8th Workshop on RTL and High Level Testing - WRTLT'07. Beijing, P.R.China, Oct. 12-13, 2007, pp.105-110.

2006

1.      G.Jervan, Z.Peng, T.Shchenova, R.Ubar. A Hybrid BIST Energy Minimization Technique for SoC Testing. IEE Proceedings on Computers & Digital Techniques, July 2006, Vol. 153, Issue 4, pp.208-216.

2.      G.Jervan, R.Ubar, Z.Peng. Hybrid BIST Methodology for Testing Core-Based Systems. Proc. of the Estonian Academy of Sciences. Engineering, 12 (2/3), pp.300-322.

3.      P.Ellervee, J.Raik, K.Tammemäe, R.Ubar. Environment for FPGA Based Fault Emulation. Proc. of the Estonian Academy of Sciences. Engineering 12 (2/3), pp.323-335.

4.      G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. J. of Computer Science and Technology. Nov. 2006, Vol. 21, No. 6, pp. 907-912.

5.      T.Bengtsson, A.Jutman, S.Kumar, Z.Peng, R.Ubar. Off-line Testing of Delay Faults in NoC Interconnects. Proceedings of the 9th IEEE EUROMICRO Conference on Digital Systems Design DSD2006, Katvat, Croatia, 2006, pp.677-680.

6.      J.Raik, R.Ubar. T.Viilukas. High-Level Decision Diagram based Fault Models for Targeting FSMs. Proceedings of the 9th IEEE EUROMICRO Conference on Digital Systems Design DSD2006, Katvat, Croatia, 2006, pp.353-358.

7.      V.Govind, J.Raik, R.Ubar. An External Test Approach for Network-on-Chip Switches. IEEE Asian test Symposium. 2006, Fukuoka, Japan, pp.437-442.

8.      M.Kruus, R.Ubar. Success Story of the Computer Engineering Department at the Tallinn University of Technology in EU Projects. The Parliament Magazine. No. 234, 13. Nov. 2006, pp.33.

9.      R.Ubar, J.Raik, A.Jutman, P.Ellervee. Digital Electronics Design and Test at Computer Engineering Department of Tallinn University of Technology. The House Magazine. The Parlamentary Weekly, No 1198, Vol.32, Dec.11, 2006, pp.42.

 2005

1.      J.Raik, R.Ubar, S.Devadze, A.Jutman. Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. Lecture Notes in Computer Science, Vol. 3463, Springer Verlag, Berlin, Heidelberg, New York 2005, pp. 332-344.

2.      J.Raik, T.Nõmmeots, R.Ubar. A New Testability Calculation Method to Guide RTL Test Generation. Journal of Electronic Testing: Theory and Applications – JETTA. Springer Science + Business Media, Inc. 21, pp.73-84, 2005.

3.      R.Ubar. Decision Diagrams and Digital Test. Journal of Microelectronics Electronic Components and Materials, 35(4), 2005, pp.187 - 195.

4.      G.Jervan, R.Ubar, Z.Peng, P.Eles. Test Generation: A Hierarchical Approach. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 63-77.

5.      G.Jervan, R.Ubar, Z.Peng, P.Eles. An Approach to System Level DFT. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 91-118.

6.      A.Matrosova, A.Pleshkov, R.Ubar. Construction of the Tests of Combinational Circuit Failures by Analyzing the Orthogonal Disjunctive Normal Forms Represented by the Alternative Graphs. J. of Automation and Remote Control. Publisher: Springer Science & Business Media B.V., 66 (2), 2005, pp. 313-327.

7.      R.Ubar, T.Shchenova, G.Jervan, Z.Peng. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. Proc. of 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.2-7.

8.      J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz, W.Pleskacz. DOT: New Deterministic Defect-Oriented ATPG Tool. Proc. of 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.96-101.

9.      A.Jutman, V.Rosin, A.Sudnitson, R.Ubar, H.-D.Wuttke A System for Teaching Basic and Advanced Topics of IEEE 1149.1 Boundary Scan Standard. EAEEIE, June 2005. Best Paper Award.

10. J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Improved Fault Emulation for Synchronous Sequential Circuits. 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.72-78.

11. J.Sudbrock, J.Raik, R.Ubar, W.Kuzmicz, W.Pleskacz. Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.79-82.

12. R.Ubar. Decision Diagrams and Digital Test. 41th International Conference on Microelectronics, Devices and Materials – MIDEM 2005, Ribno at Bled, Slovenia, Sept. 14.-16, 2005, pp.15-26. Invited plenary paper.

2004

1.      R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. Hybrid BIST Optimization for Core-Based Systems with Test Pattern Broadcasting. 2nd IEEE Int. Workshop on Electronic Design, Test and Applications – DELTA’04, Perth, Australia, 28-30 January 2004, pp.3-8.

2.      R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture. 5th IEEE Latin-American Test Workshop – LATW 2004. Digest of Papers, Cartagena, Colombia, March 8-10, 2004, pp.98-103.

3.      A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. 5th European Workshop on Microelectronics Education – EWME 2004, Lausanne, April 15-16, 2004, pp. 173-176.

4.      E. Ivask, J. Raik, R. Ubar, A. Schneider. WEB-Based Environment: Remote Use of Digital Electronics Test Tools. In “Virtual Enterprises and Collaborative Networks”, Kluwer Academic Publishers, 2004, pp. 435-442.

5.      A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. In “Microelectronics Education” Kluwer Academic Publishers, 2004, pp.253-258.

2003

1.      R.Ubar. Design Error Diagnosis with Resynthesis in Combinational Circuits. Journal of Electronic Testing: Theory and Applications 19, 73-82, 2003. Kluwer Academic Publishers.

2.      R.Ubar, J.Raik. Testing Strategies for Networks on Chip. In “Networks on Chip” by A.Jantsch, H.Tenhunen. Kluwer Academic Publishers, 2003, pp. 131-152.

3.      R.Ubar. Decision Diagrams and Digital Test. Proc. of the 6th International Workshop on Electronics, Control, Measurement and Signals, Liberec, Czechia, June 2-4, 2003, pp.266-273. Invited plenary paper.

4.      A.Jutman, A.Sudnitsõn, R.Ubar. Web-Based Applet for Teaching Boundary Scan standard IEEE 1149.1. Proc. of the 10th Int. Conf. MIXDES 2003, Lodz, June 26-28, 2003, pp.584-589. Best Paper Award.

5.      R.Ubar. Mapping Faults in Hierarchical testing of Digital Systems. Proc. of the Int. Conf. On Computer, Communication and Control technologies – CCCT’03. Orlando, USA, July 31 – August 2, 2003, pp.14-19. Best Paper Award.

6.      V.Hahanov, R.Ubar, S.Hyduke. Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. Proc. of EUROMICRO Symposion on Digital System Design - DSD’2003. Belek-Antalaya, Turkey, September 3-5, 2003, pp. 370-377.

7.      G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. 18th Int. Symposium on Defect and Fault Tolerance in VLSI Systems. Cambridge, MA, USA, November 3-5, 2003.

8.      G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003, Xi’an, China, November 17-19, 2003, pp. 318-323.