1. ESPRIT Action EUROPRACTICE (1995 - )
2. ESPRIT III BRA-6575 (1994-96)
3. Bilateral Estonian-Finnish project (1996)
5. COPERNICUS JEP 9624 (1994-97)
6. Bilateral Estonian-Swedish project (1996-97)
7. Contract No 6412 with Institute of Cybernetics, Estonia (1996-97)
8. INCO-COPERNICUS JEP 9601/70 (1996-98)
9. Estonian Science Foundation (ESF) Grant 2104 (1996-98)
11. Bilateral German - Estonian project EST-008-96 (1997-1999)
12. Bilateral Swedish -Estonian project (1999-2000)
13. INCO-COPERNICUS JEP 977133 (1998-2001)
14. Bilateral German - Estonian project (1999-2001)
15. ESF grant: 3658 (1999-2002)
16. Bilateral German-Estonian project (2000-2002)
17. ESF grant: 4003 (2000-2003)
1. ESPRIT Action EUROPRACTICE (1995 - )
Title: Promotion of professional VLSI design software in Estonia
Principal investigator: prof. R.Ubar
Financial support: continuous support in maintaining CAD SW
Abstract: The EUROPRACTICE membership has made it possible for Tallinn Technical University to purchase the professional CAD software at low prices, has given estonian students and engineers access to the western microelectronics technology and has given the possibility to start in Estonia VLSI design activity with the same tools and in the same environments as it is taking place in the western Europe, creating in such a way real basis for cooperation with the western countries in the form of subcontracts or joint projects. Based on the created environment new education curricula has been developed [1], new teaching software has been created [2], and new research results have been obtained in fault tolerance estimation [3], test pattern generation for digital systems [4-6], and fault simulation [8]. As a recognition of the R&D level reached by the department, the most important Scandinavian event NORCHIP conference sponsored by IEEE was moved to Tallinn in 1998 which was organized by the department with publishing a special issue of a Journal Analog Integrated Circuits [7].
Publications:
Title: Advanced Test Generation and Testable Design Methodology for Sequential Circuits (ATSEC)
Principal investigator: prof. R.Ubar
Financial support: 30 keuro
MSc dissertation: Jaan Raik (1997)
Abstract: Basic investigations in the field of hierarchical test generation for digital systems in a very close cooperation with western partners were carried out. A new constraints-based hierarchical automatic test pattern generator for digital systems was developed [1-4]. The novel feature of the generator was in mixing deterministic and random approaches, where high-level test planning was carried out by deterministic algorithms, and low level logic constraints were solved by simulation of random patterns.
Aplication: The test generator developed in this project showed very high performance and quality in generating test for RISC type processors [3].
Publications:
3. Bilateral Estonian-Finnish project (1996)
Title: Digital Encryption Standard Macroblock
Principal investigator: J.Põldre
Partner: Fincitec OY Finland
Financial support: 50 kEEK
Abstract: In this project a VLSI circuit with 8 bit IO implementing Digital Encryption Standard was developed. The required delivery format for customer was RTL level synthesizable VHDL code.
Applications: The device has been implemented in road toll systems for highways in Europe.
Publications:
Title: East European Microelectronics Cooperation Network of Support and Competence Centres (EEMCN)
Principal investigator: prof. R.Ubar
Financial support: 20 keuro
Abstract: The goal of the project was to build up a European research network for carrying out the following activities: demonstrating advanced microelectronic applications, transferring new technologies into the national SMEs, qualifying engineers and researchers of the SMEs by teaching and training, and running joint research projects. As the result of this project, new tools for low-level fault simulation and test generation were developed [1-3,4] which later were introduced into teaching and training curricula at Tallinn Technical University.
Publications:
Title: Functional Test Generation and Diagnosis (FUTEG)
Principal investigator: prof. R.Ubar
Financial support: 20 keuro
MSc dissertations: Priidu Paomets, Gert Jervan (1998)
Abstract: The goal of the project was to carry out a joint research on development of new methods and software for diagnosis of digital systems. New algorithms and software was developed for functional test pattern generation. Especially was investigated the case of Finite State Machines, where a new hierarchical approach for test generation based on Binary Decision Diagrams (BDD) was developed [1]. This model was generalized for using it to test complex VLSI devices [2-4]. On the model of structurally synthesized BDDs new algorithms and software for macro-level multi-valued simulation [5] and test generation [6] were developed. The algorithms run faster compared to the traditional gate-level algorithms.
Application possibilities: Since the interface has been developed between the automated test pattern generator (ATPG) and conventional design description standard in VLSI, the possibility is available for using the ATPG in connection with commercial CAD systems like Synopsys, Mentor Graphics and Cadence.
Publications:
Title: Generic VHDL Descriptions for BIST
Principal investigator: prof. R.Ubar
Partner: Jonköping University, Sweden
Financial support: 50 kEEK
Abstract: The goal of the project was to develop generic synthesizable VHDL descriptions for including controlled Built-In Self-Test (BIST) structures to digital designs. The approach is referred to as Embedded Test Processors (ETP). The ETP architecture corresponds to the IEEE Boundary-Scan standard 1149.1. In the implemented method, the application of test patterns from an internal memory will be provided. For measuring the quality of BIST [1] and testability features of circuits [2], a set of tools was developed.
Applications: The results were used in R&D projects of Jonköping University with industry in Sweden
Publications:
Principal investigator: J.Põldre
Partner: Institute of Cybernetics, Estonia
Financial support: 100 kEEK
Applications: The prototype of the chip was manufactured in the silicon foundary ES2 through EUROPRACTICE.
Financial support: 19 keuro
Abstract: In this project the curricula in the field of digital electronics and diagnostics at the Technical University of Tallinn was updated [1]. In the frame of the project the diagnostic software of Turbo-Tester (TT) was developed and introduced into teaching process at TTU and in several other European universities (at project partners) [2,3]. The low-level test methods implemented in TT where generalised with the goal of using them for high-level test generation [4,5]. Based on the professional CAD hardware and software set up in the department, a Design and Test Center for supporting new courses of teaching system dependability issues was created [6,7].
Applications: The Turbo-Tester software has been used in teaching at the University of Jonköping (Sweden), Chalmers University of Technology in Göteborg (Sweden), University of Technology in Helsinki (Finland). It was used also in teaching the students of Michigan University (USA), and engineers at the company DIGSIM DATA AB in Linköping (Sweden).
Publications:
Title: Experimental environment for innovative design and scientific studies in digital electronics
Principal investigator: prof. R.Ubar
Financial support: 445 kEEK
PhD dissertations: H. Krupnova, J. Dushina (1999)
Abstract: An experimental environment and infrastructure on the basis of professional CAD systems CADENCE, SYNOPSYS, XILINX, SOLO-1400, HILO, ALTERA, ASYL+ and on the basis of experience of using them was developed. The environment enables electronics engineers and computer scientists to experiment with new IT design and test ideas and architectures with professional tools and hardware. Testing of the environment was carried out through development projects on cryptography and research in the field of design and test. New results were obtained in test generation [1,7], ASIC prototyping [2], design verification and error diagnosis [3,4,8], simulation and fault tolerance [5,6,9].
Applications: A cryptoprocessor was developed and prototyped in a manufactury in West-Europe using this environment. The processor was the first VLSI circuit designed in Estonia. Four new courses for engineers and students were developed on this environment.
Publications:
Title: Hierarchical methods for diagnostic analysis of digital systems
Principal investigator: prof. R.Ubar
Financial support: 573 kEEK
Abstract: A new generalized diagnostic model for representing digital systems based on decision diagrams was developed. Based on this model, a novel multi-valued simulation method for gate-level digital ciruits was implemented [1.2,5-7]. The method allowed to generalize gate-level simulation algorithms for macros, and to increase thanks to lower complexity of the model considerably the speed of simulation. An automated mixed-level test pattern generator operating on register-transfer level (RTL) and gate-level representations of digital systems was developed [3,4,8]. The system implements a novel test generation approach based on a uniform diagnostic model of a digital system for mixed-level representations in form of decision diagrams. The approach allows to define a general fault model which uniformly covers high-level functional and low-level stuck-at fault models, and to apply standardized procedures for fault activation, fault propagation and line justification on both levels. On the basis of this approach a very fast hierarchical automated test pattern generator (ATPG) DECIDER was developed [9-10, 12-14]. For a specific class of tasks the ATPG is faster than known from literature found analogical ATPGs. Commercial ATPGs of such type are missing. A new method for single gate design error diagnosis was developed in a cooperation with TIMA Laboratory in Grenobel which is faster than a known SW tool [11].
Application: The hierarchical ATPG for digital systems DECIDER has been demonstrated in several exhibitions (CeBIT, Estonian Innovation Exhibition etc.). Since commercial SW tools for hierarchical test generation are missing, there is a possibility to find for DECIDER a wider application. Till now it has been used for testing industrial complex circuits at the Fraunhofer Institute of Integrated Circuits in Dresden (Germany), and in research experiments in cooperation with researchers from Sweden, Germany and Italy.
Publications:
Partner: Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden
Financial support: 400 kEEK
MSc dissertation: Eero Ivask (1998)
Abstract: A novel FPGA design flow combined with automated hierarchical test pattern generation was developed and experimented on a real FPGA circuit for telecommunication [7,8]. A hierarchical test generator for digital systems described in VHDL was implemented and integrated with the FPGA design flow used at the Fraunhofer Gesellschaft, Institute of Integrated Circuits in Dresden, Germany [1-3]. The ATPG combines bottom-up and top-down approaches to make hierarchical test generation more efficient. Both, register-transfer (RT) and gate level descriptions are used. It combines RT level deterministic test planning with gate-level local test generation based on deterministic approach at the bottom-up working mode or on random approach at the top-town working mode. Decision Diagrams (DD) are exploited as a uniform model for describing systems at both levels. A method for synthesis DDs from VHDL descriptions was developed in cooperation with INPG in Grenoble [4-6]. New high-speed register transfer level level simulator based on vector DDs was developed in cooperation with Fourier University in Grenoble [9].
Applications: The ATPG was used at the FhG Institute of Integrated Circuits in Dresden in testing industrial telecommunication VLSI designs. Experimental results have shown the advantages of using structural tests generated by ATPG compared to using functional test sequences created by designer.
Publications:
Title: Design and Test of Dependable Electronic Systems
Principal investigator: prof. R.Ubar
Partner: Linköping University
Financial support: 130 kEEK
Abstract: A new approach and the implementation of several algorithms to speed up gate-level timing simulation was proposed where instead of gate delays path delays for tree-like subcircuits (macros) are used [1,3]. Therefore timing waveforms are calculated not for all internal nodes of the gate-level circuit but only for outputs of macros. The macros are represented by structurally synthesized binary decision diagrams (SSBDD) which enable a fast computation of delays for macros. The new approach to speed up the timing simulation is supported by encouraging experimental results. A new hybrid BIST solution for testing systems-on-chip was developed [2]. It combines pseudorandom test patterns with stored precomputed deterministic test patterns. A method is proposed for finding an optimal balance between pseudorandom and stored test patterns to perform core test with minimum cost of both, time and memory, and without losing in test quality. To speed up the optimization procedure, a method is proposed for approximate estimation of the expected cost for different possible solutions with very low computational overhead.
Publications:
Title: Microelectronics Virtual Laboratory for Cooperation in Research and Knowledge Transfer (VILAB)
Principal investigator: prof. R.Ubar
Financial support: 49 keuro
Abstract: The main objective of the project is aimed at setting up and maintaining an East-West Virtual Laboratory (VL) for promoting cooperative research, development and training activities between the partner institutions in CEE and EC countries in design of dependable microelectronics systems, which is one of the most dynamically developing application fields. VL can be seen as an implementation of a Research Network based on advanced information technologies (IT). A new approach to design error diagnosis for combinational circuits in cooperation with TIMA Grenoble has been developed [1]. It allows to map classical implementation oriented diagnostic results in stuck-at fault language to design error language. As a result, classical digital test tools can be used in the field of design error diagnosis. ATPG DECIDER developed at the department was updated to achieve higher performance [2,3,4]. The simulation algorithms used in the ATPG were adjusted for cycle-based simulation in cooperation with Fourier’ University in Grenoble [5]. A new fault model was developed in cooperation with researchers from Poland, Slovakkia and Germany for estimating the coverage of physical defects by hierarchical defect simulation [6-8]. At the higher level we use the new functional fault model, at the lower level the defect/fault relationships in form of defect coverage table and conditional defect probabilities. We showed that in the worst case a test with 100% expected stuck-at fault coverage may have only 47% coverage for internal shorts in complex CMOS gates. We showed also that classical test coverage calculation methods which do not take into account the defect probabilities may lead to considerable overestimation of results.
Publications:
Title: Distance Learning on Digital Systems
Principal investigator: prof. R.Ubar
Partner: Technical University Ilmenau
Financial support: 200 kEEK (1999, 2000)
Abstract: A conception has been set up how to combine learning, training and research phases in a laboratory course for educating today’s VLSI and system designers [1,2]. Then we developed a method and Java applets based software to implement in the introductory phase of teaching interactive learning on the basis of internet modules - "living pictures" [3,4]. Further on, the hands-on training phase follows where commercial design tools and low-cost in-lab-made test oriented tools are used for solving real engineering tasks with close relationship to not yet solved research problems.
Publications:
Title: Digital Electronics Design & Test Virtual Laboratory
Principal investigator: prof. R.Ubar
Financial support: 326 kEEK (1999, 2000)
MSc dissertation: Artur Jutman (1999)
Abstract: The main goal is to create a virtual internet based electronics design and test laboratory, and to prove its vitality by increasing the efficiency of the R&D work in design and test of digital circuits and systems. Originality and novelty of the project idea is in creating a novel Web-based CAD environment in the form of an international virtual laboratory. Investigations have been carried out for possible solutions to create internet based design environment. Corresponding networking software, web-server extensions and user-tools interfaces have been developed. By using this environment cooperative experimental researh has been carried out. New results have been obtained in high-level test generation by increasing the efficiency of algorithms [1], and by implementing the ideas of concurrency [6] and genetics [7]. A new method in cooperation with TIMA Grenoble for design error diagnosis in digital circuits that doesn’t use any error model was developed [2-4]. For representing the information about erroneous signal paths in the circuit, stuck-at fault model is used. This allows to adopt the methods and tools of fault diagnosis used in hardware testing for using in design error diagnosis. Contrary to other published works, the necessary re-synthesis of the extracted subcircuit need not be applied to the whole function of an internal signal in terms of primary inputs, but may stop at arbitrary nodes inside the circuit. As the subcircuits to be redesigned are kept as small as possible, the redesign procedure is simple and fast. A new class of DD representation, called Register-Oriented DDs (RODD) has been introduced [5]. The model appeared to be an efficient and compact representation of the system behavior for high-level cycle simulation. In order to fully exploit the advantages of RODDs, new simulation algorithms which are a combination of cycle-based forward event-driven and recursive back-tracing techniques were proposed. The higher speed of simulation in comparison with commercial tools was shown by cooperative experiments with researchers from Fourier’ University in Grenoble.
Publications:
16. Bilateral German-Estonian project (2000-2002)
Title: Functional Built-in Self-Test in Digital Systems
Principal investigator: prof. R.Ubar
Partners: FhG Institute of Integrated Circuits, Dresden and University Stuttgart
Financial support: 120 kEEK (2000)
Abstract: In this project we have investigated the main trends in the field of Functional Built-In Self-Testing (BIST) and we have planned to develop a new method based on the joint competences of the partners of the project. The target of the project is to develop a new method of BIST which exploits the functionality of the system under test itself. Currently we are investigating which extentions are needed to introduce into the Automated Test Pattern Generator (ATPG) to be used in developing this new BIST method. Some new features concerning the defect-orientation in test pattern generation have been investigated in [1,2] with the goal to increase the quality of tests to be generated.
Publications:
17. ESF grant: 4003 (2000-2003)
Title: Design Error Diagnosis in Digital Circuits and Systems
Principal investigator: prof. R.Ubar
Financial support: 133 kEEK (2000)
Abstract: The main goal is to develop new efficient methods, algorithms and tools for design error diagnosis in digital circuits and systems, and to integrate these tools into commercial CAD environments. A theoretical basis for using the traditional hardware test generation methodology based on the stuck-at fault model for design verification and design error diagnosis has been developed [1,2]. The model of decision diagrams has been generalized for using it at higher levels of digital sytems presentation to increase the simulation performance in solving the tasks of verification and error diagnosis [5]. Two new types of diagrams were introduced: vector decision diagrams (VDDs) and compressed VDDs as an efficient and concise model of the system behavior, which preserves all the advantages of the decision diagrams. The experimental results of the comparison of different types of DDs as well as of different simulation algorithms on DDs have shown the efficiency of the new approach.
Publications: