Head of the Chair: Prof. Raimund Ubar

Staff of the Chair
Environment
International Cooperation
East-West Virtual Laboratory
Teaching
Research and Development
International Organizational Work
Data about the chair
Projects currently running

• Laboratory Environment
• Software Developed in the Laboratory
• Current research projects
• Main Teaching Courses
• MSc and Diploma Thesis
• Recent Most Significant Publications

Staff of the chair:

• Teet Evartson, ass. prof., cand. of techn. Sc.
• Harri Mägi, ass. prof., cand. of techn. Sc.
• Jaan Raik, PhD student
• Marina Brik, PhD student
• Priidu Paomets, PhD student
• Eero Ivask, PhD student
• Artur Jutman, MSc student
• Jüri Põldre, engineer
• Elmet Orasson, engineer
• Marek Mandre, engineer

International cooperation
When looking for financial support for the development work described above, the staff of the chair has been successful in getting grants for seven European Joint Projects under following programmes: TEMPUS (1992-1995), EUROCHIP/EUROPRACTICE (starting from 1993), PECO (1993-1995), COOPERNICUS (1994-1997), ESPRIT (1994-1996). In the present moment the chair is participating in two new INCO-COOPERNICUS projects.
The chair has cooperational links with more than 30 universities and research institutions in Europe and USA, like TU Darmstadt and TU Dresden in Germany, Joseph Fourier University and TU Grenoble in France, TU Torino in Italy, Universities of Linkoeping and Jonkoeping in Sweden, TU of Helsinki in Finland, Institute of Integrated Circuits of the Fraunhofer Society in Dresden (Germany) a.o.
Many of students who have had a postgraduate education at the chair are continuing now their studies at internationally highly recognized universities in France, Sweden, Japan, Australia, or working for USA companies. This aspect reflects the good educational basis these students have taken from the TU Tallinn, but, on the other hand, the high mobility of the staff makes the development work at the chair rather difficult.
With the Joseph Fourier University a contract has been set up for co-supervising the doctoral study with possible defence of the thesis and getting PhD degrees from both universities.
Other main activities in international cooperation are: participating in joint projects, mobility of staff and students, joint publications,  mutual reviewing of PhD theses, exchange of teaching materials and software etc.

East-West International Virtual Laboratory
A new European project has been set up to create a Virtual Laboratory for cooperation in research, teaching and knowledge transfer between nine Eastern and Western universities in the field of electronics and computer engineering. The Design&Test Center at the chair will be one corner stone of this international laboratory.
The main objective of the project is aimed at setting up and maintaining a virtual environment for promoting cooperative research and training activities between the partner institutions in design of dependable microelectronics systems, which is one of the most dynamically developing application fields today.
The Virtual Laboratory will offer a new quality in cooperative R&D and teaching by facilitating immediate exchange of information, sharing of software tools and courses developed by partners, enabling joint work on research projects and practical designs, providing access to microelectronics component libraries, benchmark circuits, design examples etc. available at partners, and serving as a source of information not only for partners, but also to all other interested persons and institutions, including national industries with a special emphasis on SMEs. For these purposes the Internet-based and multimedial tools and organizational procedures will be developed.
Three lines of complementary actions are foreseen:

• developing the concept and setting up the Research Network environment,
• cooperative R&D and teaching/training activities supported by virtual resources of this environment, and
• making the R&D results visible to the outside world by organizing User Forums and publishing regularly electronic newsletters.

Teaching
The development plan in teaching is closely related to reconstruction plans of the university which has set up a three-staged study leading to bachelor, master and doctoral degrees. For all these degree studies, new courses have been created or existing ones have been updated. The chair is responsible to develop and maintain courses in computer hardware and diagnostics.
The quality of the course development work of the chair has been successful and has found international recognition. The new lecture courses “Digital systems testing and diagnostics” and “Design for Testability” are supported  by a series of laboratory works based on the new software Turbo-Tester which has been developed by the staff members and students in co-operation.
The goal of teaching is to train in students problem-solving, team-working and self-learning skills. The conception of “learning by doing” highly recognized in teaching computer aided design at western universities has been introduced also in some of courses maintained by the chair. Successful implementation of this conception is facilitated by easy access to professional design tools and by close co-operation between researchers and students in the laboratory.
The methodology of teaching test issues, the concepts of the new laboratory course and the corresponding teaching software Turbo-Tester have been presented in about 10 papers at two European methodological conferences devoted to teaching of microelectronics design, at two European methodological EUROCHIP Workshops on VLSI Design Training, at NORCHIP and Baltic Electronics professional conferences and in several other international journals or books.
Especially for the students from abroad, the following courses with corresponding teaching material have been developed by the staff of the chair:

• LIF 3971 Digital systems testing and diagnostics (R. Ubar) - in english, german or finnish,
• Design for Testability (R.Ubar) - in english, german or finnish,
• LIF 5931 Digital Design Based on FPGAs (T. Evartson) - in english or finnish,
• VLSI Design by SYNOPSYS and CADENCE (J.Pôldre) - in english or finnish

Research and Development

The main research activities carried out in recent years by the staff and students at the chair are as follows:

• implementing decision diagrams in test synthesis and diagnosis of digital systems,
• development of new methods for hierarchical test generation based on deterministic,
• random and genetic approaches,
• development of new approaches to fault simulation and fault diagnosis,
• development of new methods and algorithms for estimating the fault-tolerance of systems,
• investigations on verification and error design diagnosis,
• investigations on design for testability,
• development of CAD software tools for automatization of test design, and
• development activities in microelectronics design.

• Hierarchical Automated Test Pattern Generator for testing digital systems and debugging digital designs, and
• a set of tools Turbo-Tester for teaching systems dependability issues.

International Organisational Work
The staff of the chair has been involved in editorial work at journals like the Journal of Analog Integrated Circuits and Signal Processing, Journal of Baltic Electronics.
They have been participated as members of programme committees annually of about 6-8 different international conferrences like European Test & Design Conference, European Conference on Dependable Computing, European Test Workshop, European Workshop on Dependable Computing, IEEE NORCHIP conference, Electronic Circuits and Systems Conference, Workshop on Mixed Design of ICs and Systems,  Baltic Electronics Conference etc.
The chair is participating in the work of international committes and societies like European Test Technology Technical Committee, IEEE Education and Computers Societies, IEEE Technical Council on Software Engineering, Society of Information Technology in Germany, Association for Computing Machinery, EU assotiation EUROPRACTICE, in steering committees of the European Dependable Computing Conference and Baltic Electronics Conference.

Data about the Chair

Laboratory environment:
a) Research Lab(digital design and test)

Hardware:

• 9 PC/compatibles with 17" monitors (mostly pentiums)
• 4 Sun workstations with 19" monitors (Sparc5-s/Sparc2powerups)
• HP Laserjet 5M network printer

• Windows95/NT (5/4) & Linux on all PC/compatibles. All PC-s have dual operating systems (Linux as X-Terminal providing software)
• Solaris 2.5.1 on all Sun-s
• CAD software: Cadence, Synopsys, Xilinx

Hardware:

• 3 PC/compatibles with 17" monitors, based on 486 processor
• 6 PC/compatibles with 17" monitors, based on Pentium processor
• HP Laserjet 4 network printer

• Windows95 & Linux on all PC/compatibles
• CAD software: Cadence, Synopsys, Xilinx

Hardware:  14 Sun workstations with 19" monitors (Sparc2 -s/Sparc IPX -s)
Software:

• Solaris 2.5.1 on all Sun-s
• CAD software: Cadence, Synopsys, Xilinx

Hardware:

• 1 Sun IPX as nameserver/mailserver/router
• 1 Sun Sparc2 as fileserver (provides 9Gb space)
• 1 Sun SparcServer 20 as application/fileserver (provides 16Gb space), has 2 processors and is configured with 1.5Gb virtual memory (320Mb real)

CAD software used in the laboratory:

• Cadence IC & Systems
• Concept shematic editor
• Verilog simulator
• Preview floorplan / router
• Synopsys SECP (europractice standard package)
• VSS (VHDL system simulator)
• VHDL Debugger (simulator grafic environment)
• DC design compiler (FPGA and CMOS syntesizer)
• BC behavioral compiler
• MC Module Compiler (data-flow synthesis system)
• Xilinx: M1.5 Xilinx Place & Route

• AMS 0.6 um 2 met. kihti CMOS tehnoloogia
• Xilinx Virtex / XC4000 tehnoloogia

a) Tools for test generation and fault analysis dor digital circuits and systems

• DECIDER: a hierarchical automated test pattern generator for digital systems (for designs described hierarchically on register-transfer and gate levels with interfaces to EDIF and VHDL)
• TURBO-TESTER – a set of tools with graphical user interface for digital test synthesis and analysis (with interfaces to EDIF and ISCAS’85)
• Deterministic test pattern generator for gate-level combinational circuits (with interfaces to EDIF and ISCAS formats)
• Random test pattern generator for gate-level combinational circuits (with interfaces to EDIF and ISCAS formats)
• Genetic algorithm based test pattern generator for gate-level combinational circuits (with interfaces to EDIF and ISCAS formats)
• Test set compaction software – minimizes the number of test patterns in a test set for combinational circuits
• Hierarchical test sequence generator for finite state machines (with interfaces to EDIF, ISCAS’89 and KISS formats)
• Fault simulator for combinational and sequential circuits (with interfaces to EDIF and ISCAS formats)
• Multi-valued simulation software for hazard analysis in digital gate-level circuits (with interfaces to EDIF and ISCAS formats)
• Software for built-in self-test quality analysis for BILBO and CSTP architectures
• System for gate-level design error diagnosis in combinational circuits (with interfaces to EDIF and ISCAS formats)
• Simulator of test experiments for analysing design error cases

• Test Pattern Converter – for converting high-level test patterns of DECIDER into gate-level level test patterns
• RTL VHDL/DD interface - a tool for converting Register-Transfer Level (RTL) VHDL descriptions into Decision Diagram (DD) form
• EDIF/SSBDD interface - a tool for converting EDIF netlists into SSBDD (Structurally Synthesized BDD) models
• ISCAS’89/EDIF interface – a tool for converting ISCAS’89 netlists into EDIF netlists
• EDIF /ISCAS’85 interface – a tool for converting EDIF netlists into ISCAS’85 netlists
• EDIF /ISCAS’89 interface – a tool for converting EDIF netlists into ISCAS’89 netlists

• Library generator - a tool for generating custom technology libraries for the EDIF interface
• Functional Unit (FU) Library generator - a tool for creating FU libraries in DD, VHDL and C formats
• FU Library (DD) - Descriptions of Functional Units (FU) in Decision Diagram (DD) format (required by the RTL VHDL interface)
• FU Library (VHDL) - VHDL behavioral descriptions of Functional Units (required for high-level (CAMAD, Visual Architect) and logic synthesis (SYNOPSYS))

• Synthesis scripts - Scripts for logic synthesis of hierarchical designs with SYNOPSYS.

a) Joint European projects:

1. INCO-COPERNICUS JEP 9601/70 SYTIC “Promotion of System Design Training and Information Centers in CCE/NIS” (1997-1999)
2. INCO-COPERNICUS JEP 977133 VILAB “Microelectronics Virtual Laboratory for Cooperation in Research and Knowledge Transfer” (1998-2001)

1. EST-008-96 “Automated Test Generation for FPGA based Designs” (1996-1999). Partner: Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden.

1. Hierarchical Methods of Test Synthesis for Digital Systems. Grant G-1850 (1996-1999).
2. Digital Electronics & Test Virtual Laboratory. Grant G-3658 (1999-2002).

1. Computers I and II
2. Field Programmable Gate Arrays
3. Diagnostics of Digital Systems
4. Design for Testability

MSc and Diploma Thesis:

a) MSc Thesis:

• J. Raik. Hierarchical Test Generation Based on Alternative Graph Models. TTU, 1997.
• E. Ivask. Genetic Algorithms in Test Pattern Generation. TTU. 1998.
• G. Jervan. Decision Diagram Synthesis from VHDL. TTU. 1998.
• P. Paomets. An Open and Dynamic User Interface to the CAD System Turbo-Tester. TTU, 1998.
• J. Põldre. Cryptoprocessor PLD001. TTU, 1998.

• J.Raik, R.Ubar. Hierarchical Test Generation for Digital Systems Based on Combining Bottom-Up and Top-Down Approaches. World Multiconference on Systemics, Cybernetics and Informatics. Orlando, Florida, July 12-16, 1998, Vol.1, pp. 374-381.
• E.Ivask, J.Raik, R.Ubar. Comparison of Genetic and Random Techniques for Test Pattern Generation. Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 163-166.
• G.Jervan, A.Markus, J.Raik, R.Ubar. VHDL Based Test Generation System. Proceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 1998, pp.145-148.
• G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Turbo Tester: A CAD System for Teaching Digital Test. In "Microelectronics Education". Kluwer Academic Publishers, pp.287-290, 1998.
• A. Buldas, J.Põldre. A VLSI implementation of RSA and IDEA encryption engine. 15th NORCHIP Conference, Tallinn, November 10-11, 1997, pp. 281-288.

• L. Raun. Diagnostic Analysis of Digital Systems. I. TTU, 1998.
• J. Heinlaid. Diagnostic Analysis of Digital Systems. II. TTU, 1998.
• A. Markus. Test Pattern Compaction in Combinational Circuits. TTU, 1998.

• A.Markus, J.Raik, R.Ubar. Test Set Minimization Using Bipartite Graphs. Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 175-178.
• R.Ubar, J.Heinlaid, J.Raik, L.Raun. Calculation of Testability Measures on Structurally Synthesized Binary Decision Diagrams. Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 179-182.

1. Guest Editorial (T-S.Lande, R.Ubar). Analog Integrated Circuits and Signal Processing. Kluwer Publishers, Vol.18, No 1., January 1999, pp. 5-6.
2. Single Gate Design Error Diagnosis in Combinational Circuits (R.Ubar, D.Borrione). Proceedings of the Estonian Acad. of Sci. Engng, 1999, Vol. 5 , No 1, pp. 3-21.
3. Combining Functional and Structural Approaches in Test Generation for Digital Systems  (R.Ubar). Journal of Microelectronics and Reliability, Elsevier Science Ltd., Vol. 38:3, pp.317-329, 1998.
4. Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams (R.Ubar). Multiple Valued Logic, Overseas Publishers Assotiation N.V., Vol.4,  pp.141-157, 1998.
5. Dynamic Analysis of Digital Circuits with 5-valued Simulation (R. Ubar). In "Mixed Design of Integrated Circuits and Systems". Kluwer Acad. Publishers, pp.187-192, 1998.
6. Hierarchical Test Generation for Digital Systems (M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar). In "Mixed Design of Integrated Circuits and Systems". Kluwer Academic Publishers, pp.131-136, 1998.
7. Turbo Tester: A CAD System for Teaching Digital Test (G.Jervan, A.Markus, P.Paomets, J.Raik, P.Paomets). In "Microelectronics Education". Kluwer Academic Publishers, pp.287-290, 1998.
8. Feasibility of Structurally Synthesized BDD Models for Test Generation (J.Raik, R.Ubar). Proc. of the IEEE European Test Workshop, Barcelona, May 27-29, 1998, pp.145-146.
9. Hierarchical Test Generation with Multi-Level Decision Diagram Models (G.Jervan, A.Markus, J.Raik, R.Ubar). Proc. of the 7th IEEE North Atlantic Test Workshop,  West Greenwich RI, USA, May 28-29, 1998, pp.26-33.
10. Mixed Bottom-Up/Top-Down Hierarchical Test Generation for Digital Systems (R.Ubar). Proc. of the 9th European Workshop on Dependable Computing, Gdansk (Poland), May 14-16, 1998, pp.37-40.
11. Synthesis of Decision Diagrams from Clock-Driven Multi-Process VHDL Descriptions for Test Generation (R.Leveugle, R.Ubar). Proc. of the 5th International Conference on Mixed Design of Integrated Circuits and Systems. Lodz (Poland), June 18-20, 1998, pp. 353-358. Best Paper Award.
12. Hierarchical Test Generation for Digital Systems Based on Combining Bottom-Up and Top-Down Approaches (J.Raik, R.Ubar). World Multiconference on Systemics, Cybernetics and Informatics. Orlando, Florida, July 12-16, 1998, Vol.1, pp. 374-381.
13. Dynamic Analysis of Digital Circuits with Multi-Valued Simulation (R. Ubar). Microelectronics Journal, Elsevier Science Ltd., Vol. 29, No. 11, Nov. 1998, pp.821-826.
14. Generation of Tests for the Localization of Single-Gate Design Errors in Combinational Circuits Using the Stuck-at Fault Model (R.Ubar, D.Borrione). Proc. of the 11th IEEE Brasilian Symp. on IC Design. Rio de Janeiro, Brazil, Sept. 30 – Oct. 3, 1998, pp.51-54
15. Teaching Dependability Issues in System Engineering at the Technical University of Tallinn (R.Ubar). Global J. of Engineering Education, Vol.2, No 2, 1998 UICEE, Printed in Australia, pp. 215-218.
16. A New Approach to Build a Low-Level Malicious Fault List Starting from High-Level Description and Alternative Graphs (R. Ubar et al.). Proc. IEEE European Design & Test Conference, Paris, March 17-20, 1997, pp.560-565.
17. Multi-Valued Simulation with Binary Decision Diagrams (R.Ubar, J.Raik). Proc. IEEE European Test Workshop, Cagliari (Italy), May 28-30, 1997, pp.28-29.
18. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments  (A.Benso, P.Prinetto, M.Rebaudengo, M.Sonza Reorda, J.Raik, R.Ubar). 1997 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems. Paris, October 20-22, 1997, pp. 212-216.
19. Assembling Low-Level Tests to High-Level Symbolic Test Frames (G. Jervan, A.Markus, J. Raik, R. Ubar). IEEE 15th NORCHIP Conf., Tallinn, Nov. 10-11, 1997, pp. 275-280.
20. Mixed-Level Test Generator for Digital Systems (M.Brik, G.Jervan, A.Markus, J.Raik, P.Paomets, R.Ubar). Proc. of Estonian Acad. of Sci. Engng, 1997, Vol.3 ,No4,pp.271-282.
21. Test Synthesis with Alternative Graphs (R.Ubar). IEEE Design and Test of Computers. Spring, 1996, pp.48-59.
22. Multi-Level Test Generation and Fault Diagnosis for FSMs. (R.Ubar,M.Brik). Lect. Notes in Computer Sci. No 1150. Dependable Computing. Springer-Verlag, 1996, pp.264-281.
23. Education Environment for Electronics and Microsystems (R.Ubar et al.). Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. 1996, p.145-148.
24. Low-Cost CAD System for Teaching Digital Test (R.Ubar, P.Paomets, J.Raik). Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. 1996, p.185-188
25. Electronics Competence Centre and Research in Digital Test at TU Tallinn (R.Ubar). Invited paper. IEEE 14th NORCHIP Conf., Helsinki, November 4-5, 1996, pp.134-141.