However, there are quite common situations, where the testing time is the subject of a special concern. For such cases, this basic approach is not feasible because of the large test length (and therefore the testing time). To fight this problem, we can generate very short test (with the length S << L) using external automated test pattern generators (ATPG). These generated patterns need to be stored inside the chip somewhere in a memory. In that case no LFSR is needed to generate patterns on the fly and at the same time we can have the shortest possible test. However, it will occupy much space inside the chip, because we need some dedicated memory module to store it there. So, this seems not to be an optimal solution.
There is a technique, which uses some small amount of stored test vectors and generates the most of needed vectors on the fly. It can help us in such a difficult situation. In this approach, stored patterns used as the seeds of the LFSR. Using these seeds, a set of short test sequences is generated one after another. Each sequence is generated by using the correspong seed. Taken all togeter, these sequences produce a good fault coverage. At the same time, such a BIST device does not take up much space and works remarkably faster than a conventional LFSR generator.
Suppose, we have S seeds stored in memory and for every seed i we choose the sequence of length Li. The total test length will be L=L1+L2+...+LS. An optimal solution will be such a solution where using minimal number of stored vectors S we are able to achieve required maximal total test length L which is much less than in the "only generated" case.
