1. Estonian Excellence Centre of Dependable Computing
(2003-2007)
Digital
Design and Test Research Group
2.
Design and Test of Digital Systems
Governmental Basic Financing (2003-2007)
4. ESF Grant 5910: Self-Testing
Digital Systems (2004-2007)
6.
Promotion of the use of professional CAD software at universities
7. New Methods in Digital Test. Research Professorship at the Estonian Academy of Sciences (2003-2005)
11. V Framework IST-2000-30193 REASON
Research
and Training Actionfor System on Chip Design (2002 - 2005)
12. INCO-COPERNICUS JEP
977133 VILAB
Microelectronics Virtual Laboratory for Cooperation in
Research and Knowledge Transfer (1998-2001)
13. INCO-COPERNICUS JEP 9601/70 SYTIC
Promotion of System
Design Training and Information Centers
in CCE/NIS (1996-98)
East
European Microelectronics Cooperation Network of Support and Competence Centres
(1994-1997)
Functional
Test Generation and Diagnosis (1994-97)
Advanced
Test Generation and Testable Design Methodology for Sequential Circuits
(1994-96)
17. European Thematic Network
10063-CP-1-2000-1-PT-ERASMUS-ETNE
Thematic Harmonisation in Electrical
and Information EngineeRing in Europe – THEIERE (2002-2005)
18. Promotion of the use of professional
CAD software at universities
19. MOSCITO-based Test Tool Integration for Resarch
and eLearning aided Education
Bilateral German-Estonian project (2004-2006)
20. Defect-Oriented Testing
of Digital Systems
Estonian- Polish Joint Research Project (2003-2005)
Bilateral German-Estonian project DILDIS (2002-2006)
22. Functional Built-in Self-Test in Digital Systems
Bilateral German-Estonian project (2000-2002)
Bilateral German-Estonian project DILDIS (1999-2001)
24. Bilateral Swedish-Estonian project (1999-2000)
Design
and Test of Dependable Electronic Systems
25. Bilateral Swedish-Estonian project (1996-97)
Generic
VHDL Descriptions for BIST
27. Defect-Oriented Testing of Digital Circuits
28. Design Error Diagnosis in Digital Circuits and Systems
29. Digital Electronics Design & Test Virtual Laboratory
30. Hierarchical methods for diagnostic analysis of digital
systems
31. Experimental environment for innovative design and scientific studies in digital electronics
32. Methods and Software for Testing Digital Systems
Contract with Artec Design - MIKROTEST
(2001-2003)
Estonian Excellence Centre
of Dependable Computing (2003-2007)
Digital
Design and Test Research Group
The
research team of the Computer Engineering Department belongs to one of the 10
Estonian Research Excellence Centres “Centre of Dependable Computing” forming
the research group “Digital Design and Test”. The scientific goals of our
research group are closely related to the most highly recognized guidelines for
design and test solutions of “The MEDEA Design Automation Roadmap”. MEDEA
(Micro-Electronics Development for European Applications) is a part of the
pan-European
Design and Test of Digital
Sustems
Governmental
Basic Financing (2003-2007)
The goals of the research are to investigate the
possibilities for developing new better methods for new type of digital systems
(Systems on Chip) for design and test, to develop new efficient algorithms,
methods and software for HW/SW codesign, decompositional synthesis of hardware,
simulation, low-power design, increasing fault-tolerance, test program
automated generation, fault diagnosis and for estimation and improvement of
software processes. It is planned to improve the diagnostic model of digital
systems by using high-level decision diagrams to cover broader class of faults
and to increase the working speed of algorithms by better organization and
parallelization of procedures. New hierarchical methods for test generation and
fault simulation to reach higher physical defect coverage and to increase the
speed compared to the known plain logical level methods will be developed. A
new conception, methods and software for built-in self-test of digital systems,
which use more efficiently the functional ressources of the system and reach
higher fault coverage than common methods today, will be developed. As to
system design, new methods for decomposition of behaviour description of
algorithms, and for decomposition of modules on RT level will be developed.
Combination of two decomposition methods into a single methodology will allow
extend the possibilities in search for architectural solutions and to reach
more exact results.
Governmental
Basic Financing (2007)
Accepted proposal (in Estonian)
ESF Grant 5910:
Self-Testing Digital Systems (2004-2007)
The main goal of the current project is to develop new
methods, algorithms and software tools for design of self-testing digital
systems. The main problems and objectives to be investigated are: - develoment,
evaluation and optimization of hybrid BIST architectures of digital systems; -
develoment, evaluation and optimization of functional BIST of digital systems;
- methods for BIST driven design for testability of digital systems; -
development of new methods for design of self-testing digital systems by
combining hybrid and functional BIST approaches with design for testability.
The following outcome of the project is expected: - new architectures for
implementing hybrid BIST conception in digital systems; - cost models for new
different hybrid BIST architectures; - fast and simple cost estimation
algorithms and tools for evaluation of solutions for hybrid BIST; - methods for
minimizing hybrid BIST cost at given different constraints; - new test
generation, fault simulation, test ordering and cost calculation tools and
experimental research environment for carrying out optimization procedures for
hybrid and functional BIST; - new methods of functional BIST for digital
systems; - new methods of combining hybrid and functional BIST methods with
design for testability.
Estonian-
Polish Joint Research Project (2007-2009)
Coordinator: Raimund Ubar
Testing
modern microelectronics faces two contradictory problems – accuracy and
complexity. The goal of the project is development of a hierarchical solution
that handles the complexity without compromising accuracy. Special benchmarking
hardware has to be also developed to evaluate the performance and accuracy of
different defect-oriented test generation approaches.
The main objectives of the research are: (1) analysis and
characterization of new types of physical defects; (2) fine tuning of existing
fault models as well as simulation and test generation algorithms. These
objectives will be met via utilizing the synergistic effect in the
interdisciplinary cooperation by jointly exploiting the experience of Polish
partners in lower-level modeling (modeling circuits at the transistor and
layout level) and of Estonian partners in higher-level modeling (in modeling
gate- and register-transfer-level systems). The first result of the
cooperation: a hierarchical approach based on critical area extraction
for identifying the possible shorted pairs of nets on the basis of the chip
layout information, combined with logic level test pattern generation for
bridging faults [1].
Joint
publications:
1. M.Jenihhin, J.Raik, R.Ubar, W.A.Pleskacz, M.Rakowski. Layout to Logic Defect Analysis for Hierarchical Test Generation. The 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems - DDECS 2007. Krakow, Poland, April 11-13, 2007, pp.35-40.
Project description: http://www.pld.ttu.ee/~raiub/projektid/PolEst_07_09.pdf
Promotion
of the use of professional CAD software
at universities
EUROPRACTICE
Action (1995 -)
Coordinator: Raimund Ubar
The project is
a continuation of the Action EUROCHIP with the goal to promote the use of
professional design software in Estonia; maintenance of the CAD software
systems SYNOPSIS, CADENCE, XILINX, ALTERA, to support purchasing new licences,
installing the software and introducing into the teaching process at the
Computer Engineering Department, manufacturing of the integrated circuits
designed at the university in beneficial conditions.
1. M.Ajaots, M.Min, T.Rang, R.Ubar. Education Environment for Electronics and Microsystems. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. 1996, p.145-148.
2. R.Ubar. Teaching Dependability Issues in System Engineering at the Technical University of Tallinn. Global J. of Engineering Education, Vol.2, No 2, 1998 UICEE, Printed in Australia, pp. 215-218.
3. R.Ubar, A.Jutman, E.Orasson, J.Raik, T.Evartson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. In the book "Microelectronics Education", Marcombo Boixareu Ed., 2002, pp.317-320.
4. E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, H-D.Wuttke. Research Environment for Teaching Digital Test. 49. Int. Conf. IWK, Ilmenau, Germany, September 27-30, 2004, pp.468-473.
5. M.Kruus, R.Ubar. Success Story of the Computer Engineering Department at the Tallinn University of Technology in EU Projects. The Parliament Magazine. No. 234, 13. Nov. 2006, pp.33.
6. R.Ubar, J.Raik, A.Jutman, P.Ellervee. Digital Electronics Design and Test at Computer Engineering Department of Tallinn University of Technology. The House Magazine. The Parlamentary Weekly, No 1198, Vol.32, Dec.11, 2006, pp.42.
New Methods in Digital Test. Research
Professorship at the
The goal of the
project was to carry out research in the field of Digital Test to develop new
methods, algoriths and software tools for test synthesis and analysis for
digital systems. A new
conception was developed for hierarchical modeling defects in digital systems.
As a result, the first time, a tool was created for proving redundancy of
physical defects in digital circuits. The new tool allows to evaluate the
quality of test generation more adequately than the existing tools can do. A
new hierarchical automated test pattern generator (ATPG) for digital systems
was developed. The new tool is faster and reaches the best fault coverage
compared to the known university tools whereas commercial hierarchical ATPG
tools are missing. A new research direction was opened targeted to optimization
of hybrid built-in self-test (BIST) processes and hybrid functional self-test
processes. The core of this direction consists of a new fast cost estimation
method for BIST and of a new iterative approach based on this method for
optimization of complex BIST processes.
Final presentation (in Estonian)
Co-financing of the EU Framework VI STREP project (2006)
Principal investigator: Raimund Ubar
The goal of this activity was to
support the European VI Framework project VERTIGO with co-financing the
accompanying actions not financed by VERTIGO. The activities in the project
included the introduction of the VERTIGO results into the study process at TTU
and the integration of the new prototype tools developed into the R&D and
teaching environment at TTU. An internet based training system was developed
for teaching design and test. The system allows to investigate design and test
problems at lower logic level and higher RTL and microprogram levels, it can be
used in classes, at home and during exams. Differently from analogical teaching
systems the new environment allows to investigate and analyze different design
algorithms, synthesize optimized selftesting sessions, and evaluate the
selftesting quality in digital systems. New tools for editing the design
descriptions were added to the diagnostic package Turbo Tester.
Selected publications:
1.
R.Ubar, A.Jutman, M.Kruus, E.Orasson,
S.Devadze, H.-D.Wuttke. Learning Digital Test and Diagnostics via Internet.
International Journal of Emerging Technologies in Learning. International
Journal of Online Engineering, Vol.3, No.1, pp.1-9, 2007.
2.
2. A.Jutman, A.Tsertov, R.Ubar. A Tool for
Teaching Pseudo-Random TPG Principles. 17th EAEEIE Conf. on Innovation in
Education for Electrical and Information Engineering,
Investigations, Developments and Applications in the Field of Design and Testing of Digital Systems.
Target Financed Project (1998-2002)
The goal of the project was to investigate new methods for HW/SW codesign, analysis, simulation, verification and increasing the fault-tolerance of digital systems, low-power design, automated test program generation and fault diagnosis. This list of topics describes in a compact way the research activities of the Computer Engineering Department carried out during the last five years. As the result of the project a new approach was developed for diagnostic modelling of digital systems based on decision diagrams (DD) including traditional Binary DDs (BDD), Structurally Synthesized BDDs and High-Level DDs. New methods and algorithms were developed based on this DD-approach for test generation and fault simulation which allowed to improve the efficiency of fault analysis compared to the known methods. The novelty of the new DD-based model was in creating of a uniform mathematical basis for diagnostic modelling of digital systems which allowed to cope better with the complexity problem and to increase the accuracy of simulation.
Selected publications:
1. Raik, J.; Ubar, R (2000). Fast test pattern generation for sequential circuits using decision diagram representations. Journal of Electronic Testing-Theory and Applications, 16(3), 213 - 226.
2. Ellervee, P.; Miranda, M.; Catthoor, F.; Hemani, A. (2001). System-level Data-Format Exploration for Dynamically Allocated Data Structures. IEEE Transactions on CAD, 20(12), 1469 - 1472.
3. Ubar, R. (1998). Multi-valued simulation of digital circuits with structurally synthesized binary decision diagrams. Multiple valued logic, 4, 141 - 157.
The aim of the project was to facilitate the development
of ICT cluster in
Selected publications:
1. Ubar,
R.; Kruus, M. (2006). Success Story of the Computer Engineering Department at
the
2.
Ellervee, P.; Raik, J.; Tammemäe, K.; Ubar, R. (2006).
Environment for FPGA Based Fault Emulation. Proceedings of the
3.
Novak,
O.; Gramatova, E.; Ubar, R. (2005). Handbook of Electronic Testing.
Final project
(pdf) http://www.pld.ttu.ee/~raiub/eVikings/final_report.pdf
Presentation
(pdf) http://www.pld.ttu.ee/~raiub/projektid/ev2_presentation.pdf
V
Framework IST-2000-30193 REASON
Research and Training Actionfor System on Chip Design (2002 - 2005)
The main goal of the project is to facilitate integration
of the academic and research institutions of Central and Eastern Europe (CEE) working
in the field of microelectronics into the mainstream R&D activities going
on in the EU countries. To achieve this goal, the project aimed at raising the
level of education and research as well as the number of highly-skilled
researchers and designers in the field of microelectronic design in CEE
countries, in order to facilitate co-operation in R&D, to reduce the
microelectronic skills shortage in
Selected publications:
1. R.Ubar, H-D.Wuttke. Research and Training Environment for Digital Design and Test. 34th ASEE/IEEE Frontiers in Education Conference, October 20-23, 2004, Savannah, GA, pp.S3F-18 to S3F-24. IEEE Catalog Number: 04CH37579. ISBN: 0-7803-8552-7. Library of Congress: 79-640910. ISSN: 0190-5848.
2. O.Novak,
E.Gramatova, R.Ubar. IST Project REASON – Handbook of Testing Electronic
Systems. Proc. of 5th European Dependable Computing Conf. – EDCC-5,
3. W.A.Pleskacz,
T.Borejko, A.Walkanis, V.Stopjakova, A.Jutman, R.Ubar. DefSim: CMOS Defects on
Chip for Research and Education. 7th IEEE Latin-American Test Workshop, March
26-29, 2006,
Final report
(pdf) http://www.pld.ttu.ee/~raiub/projektid/R_final_report.pdf
Presentation
(pdf) http://www.pld.ttu.ee/~raiub/projektid/R_presentation.pdf
Teaching system
DefSim http://defsim.testonica.com
INCO-COPERNICUS JEP 977133 VILAB
Microelectronics
Virtual Laboratory for Cooperation in Research and Knowledge Transfer
(1998-2001)
The main objective of the project was aimed at setting up
and maintaining an East-West Virtual Laboratory (VL) for promoting cooperative
research, development and training activities between the partner institutions
in CEE and EC countries in design of dependable microelectronics systems, which
is one of the most dynamically developing application fields. VL can be seen as
an implementation of a Research Network based on advanced information
technologies (IT). A new approach to design error diagnosis for combinational
circuits in cooperation with TIMA Grenoble has been developed. It allows to map
classical implementation oriented diagnostic results in stuck-at fault language
to design error language. As a result, classical digital test tools can be used
in the field of design error diagnosis. ATPG DECIDER developed at the
department was updated to achieve higher performance. The simulation algorithms
used in the ATPG were adjusted for cycle-based simulation in cooperation with
Fourier’ University in
Selected publications:
1. R.Ubar, A.Morawiec,
J.Raik. Cycle-Based Simulation Algorithms for Digital Systems Using High-Level
Decision Diagrams. IEEE Proc. of Design Automation and Test in
2. M.Blyzniuk,
T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar.
Hierarchical Defect-Oriented ault Simulation for Digital Circuits. IEEE
European Test Workshop,
3. A.Schneider,
K.-H.Diener, G.Elst, E.Ivask, J.Raik, R.Ubar. Internet-Based Testability-Driven
Test Generation in the Virtual Environment MOSCITO. Proc. IFIP Conference on IP
Based SOC Design,
Report (pdf) http://www.pld.ttu.ee/~raiub/projektid/vilab_report.pdf
Presentation (pdf) http://www.pld.ttu.ee/~raiub/projektid/vilab_present.pdf
INCO-COPERNICUS JEP 9601/70 SYTIC
Promotion of System Design
Training and
In this project the
curricula in the field of digital electronics and diagnostics at the Technical
University of Tallinn was updated [1]. In the frame of the project the
diagnostic software of Turbo-Tester (TT) was developed and introduced into
teaching process at TTU and in several other European universities (at project
partners) [2,3]. The low-level test methods implemented in TT where generalised
with the goal of using them for high-level test generation [4,5]. Based on the
professional CAD hardware and software set up in the department, a Design and
Test Center for supporting new courses of teaching system dependability issues
was created [6,7].
Applications:
The Turbo-Tester software has been used in teaching at the
Publications:
1.
M.Ajaots,
M.Min, T.Rang, R.Ubar. Education Environment for Electronics and Microsystems Microelectronics Education. World Scientific
Publishing Co. Pte. Ltd. 1996, p.145-148.
2.
R.Ubar,
P.Paomets, J.Raik. Low-Cost CAD System for Teaching Digital Test Microelectronics Education. World Scientific
Publishing Co. Pte. Ltd. 1996, p.185-188.
3.
G.Jervan,
A.Markus, P.Paomets, J.Raik, P.Paomets, R.Ubar. Turbo Tester: A CAD System for
Teaching Digital Test. In "Microelectronics Education". Kluwer Academic Publishers, 1998,
pp.287-290.
4.
R.Ubar.
Mixed Bottom-Up/Top-Down Hierarchical Test Generation for Digital Systems. Proc. of the 9th European
Workshop on Dependable Computing,
5.
G.Jervan,
A.Markus, J.Raik, R.Ubar. A Decision Diagram Based Hierarchical Test Pattern
Generator. Proc. of the 6th
Baltic Electronics Conference, Oct. 7-9, 1998,
6.
R.Ubar.
Teaching Dependability Issues in System Engineering at the
7.
R.Ubar.
Teaching Dependability Issues in System Engineering at the
East
European Microelectronics Cooperation Network of Support and Competence Centres
(1994-1997)
The goal of the project was
to build up a European research network for carrying out the following
activities: demonstrating advanced microelectronic applications, transferring
new technologies into the national SMEs, qualifying engineers and researchers
of the SMEs by teaching and training, and running joint research projects. As
the result of this project, new tools for low-level fault simulation and test
generation were developed [1-3,4] which later were introduced into teaching and
training curricula at
Publications:
1.
G.Jervan,
A.Markus, P.Paomets, J.Raik, R.Ubar. Teaching Test and Design for Testability
with TURBO-TESTER. Software Proc. of the
3rd Workshop on Mixed Design of Integrated Circuits and Systems,
2.
H.
Krupnova et. al. ASIC Prototyping for Reprogrammable Implementations of Large
ASICs. ACM/SIGDA 4th Int. Symposium on
FPGAs. Proceedings.
3.
G.Jervan,
A.Markus, J.Raik, R.Ubar. Mixed-Level Deterministic-Random Test Generation for
Digital Systems. Proc. of the 5th
International Conference on Mixed Design of Integrated Circuits and Systems.
4.
M.Brik,
R.Ubar. An Improved Test Generation Approach for Sequential Circuits using
Decision Diagrams. Proc. of the 6th
Baltic Electronics Conference, Oct. 7-9, 1998,
Functional
Test Generation and Diagnosis (1994-97)
The goal of the project was to
carry out a joint research on development of new methods and software for
diagnosis of digital systems. New algorithms and software was developed for
functional test pattern generation. Especially was investigated the case of
Finite State Machines, where a new hierarchical approach for test generation
based on Binary Decision Diagrams (BDD) was developed [1]. This model was
generalized for using it to test complex VLSI devices [2-4]. On the model of
structurally synthesized BDDs new algorithms and software for macro-level
multi-valued simulation [5] and test generation [6] were developed. The
algorithms run faster compared to the traditional gate-level algorithms.
Application possibilities: Since the
interface has been developed between the automated test pattern generator
(ATPG) and conventional design description standard in VLSI, the possibility is
available for using the ATPG in connection with commercial CAD systems like
Synopsys, Mentor Graphics and Cadence.
Publications:
1.
R.Ubar,
M.Brik. Multi-Level Test Generation and Fault Diagnosis for
2.
J.Raik,
P.Paomets. Test Synthesis from Register-Transfer Level Descriptions. Baltic Electronics Conference. Proceedings.
3.
R.Ubar.
Representing Transparency Conditions in Test Generation for VLSI by Decision
Diagrams. 1st Electronic Circuits and
Systems Conference.
4.
G.Jervan,
A.Markus, J.Raik, R.Ubar. Automatic Test Generation System for VLSI. 1st Electronic Circuits and Systems
Conference.
5.
R.Ubar,
J.Raik. Multi-Valued Simulation with Binary Decision Diagrams. Proc.IEEE European Test Workshop,
6.
J.Raik,
R.Ubar. Feasibility of Structurally Synthesized BDD Models for Test Generation.
Proc. of the IEEE European Test Workshop,
7.
G.Jervan,
A.Markus, J.Raik, R.Ubar. Hierarchical Test Generation with Multi-Level
Decision Diagram Models. Proc. of the 7th
IEEE North Atlantic Test Workshop,
Advanced
Test Generation and Testable Design Methodology for Sequential Circuits
(1994-96)
Basic investigations in the
field of hierarchical test generation for digital systems in a very close
cooperation with western partners were carried out. A new constraints-based
hierarchical automatic test pattern generator for digital systems was developed
[1-4]. The novel feature of the generator was in mixing deterministic and
random approaches, where high-level test planning was carried out by
deterministic algorithms, and low level logic constraints were solved by simulation
of random patterns.
Aplications: The test generator developed
in this project showed very high performance and quality in generating test for
RISC type processors [3].
Publications:
1.
R.Ubar.
Test Synthesis with Alternative Graphs. IEEE
Design and Test of Computers. Spring, 1996, pp.48-59.
2.
R.Ubar.
Combining Symbolic Techniques with Topological Approach in Test Generation. Proc. of the 3rd Workshop on Mixed Design of
Integrated Circuits and Systems,
3.
R.Ubar,
A.Markus, G.Jervan, J.Raik. Fault Model and Test Synthesis for RISC Processors Baltic Electronics Conference. Proceedings.
4.
J.Raik,
R.Ubar, G.Jervan, H.Krupnova. A Constraint-Driven Gate Level Test Generation. Baltic Electronics Conference. Proceedings.
Report (pdf)
European
Thematic Network 10063-CP-1-2000-1-PT-ERASMUS-ETNE
Thematic Harmonisation in Electrical and Information EngineeRing in
The aims
of this new thematic network (years 2000 to 2003) were to prepare a survey concerning
the available curricula in EIE (Electrical and Information Engineering)
throughout the whole Europe, to give a reflection on the best practices of high
engineering education in the specific field of Electrical and Information
Engineering in a European perspective, to develop pieces of curriculum and
pedagogical tools available through the internet as pre-requisites to help
students for mobility exchange programmes (ex: ECTS). The whole aim was to get
a harmonisation of the curricula in EIE throughout
Promotion
of the use of professional CAD software
at universities
EUROCHIP
Action (1993 - 1995)
The EUROCHIP membership has made
it possible for Technical University to purchase the professional CAD software
at low prices, has given Estonian students and engineers access to the Western
microelectronics technology and has given the possibility to start in Estonia
VLSI design activity with the same tools and in the same environments as it is
taking place in the western Europe, creating
in such a way real basis for cooperation with the western countries in the form
of subcontracts or joint projects.
As the result of this project and
other European projects TEMPUS, EEMCN and FUTEC, a new structural unit
Electronics Competence Centre was established at Tallinn Technical University.
Under the coordination of this centre a PLD laboratory was equipped with new
SUN workstations and with licences of the professional CAD
software systems SYNOPSIS, CADENCE, SOLO, HILO, and XILINX .
Publications:
1. R.Ubar, K.Vainomaa. Electronics Competence Centre at the Tallinn Technical University. Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.
2. R.Ubar. Electronics Competence Centre as a Result of European Projects at the Technical University of Tallinn (Ubar). J. of Baltic Electronics, Vol. 1, No. 2, Dec., 1995, pp.9-11.
3. M. Glesner, T. Hollstein, B. Courtois, P. Amblard, R. Ubar, K. Vainomaa. New Curricula and a Competence Centre through TEMPUS at the Technical University of Tallinn Proc. EC Workshop on Design Methodologies for Microelectronics, Smolenice, 1995, pp. 347-353.
4. R.Ubar. Electronics Competence Centre and Research in Digital Test at Technical University of Tallinn. Invited paper. IEEE 14th NORCHIP Conference, Helsinki, November 4-5, 1996, pp.134-141.
MOSCITO-based Test Tool Integration for Resarch and eLearning aided Education
Bilateral German-Estonian project (2004-2006)
Fraunhofer
The project was focussed on a cooperative joint high- and low-level design flow with automated test generation for developing complex digital systems. The substantial R&D goals have been addressed to achieve high testability and high quality testing by efficient test generation and fault simulation. The features of this project were: Internet based partners’ competence, partners tool integration, and contributions to hierarchical tools for test generation and fault simulation.
Selected joint publication:
1. E. Ivask, J. Raik, R.
Ubar, A. Schneider. WEB-Based Environment: Remote Use of Digital Electronics
Test Tools. In “Virtual Enterprises and Collaborative Networks”, Kluwer
Academic Publishers, 2004, pp. 435-442.
2. E.Ivask, A.Jutman,
E.Orasson, J.Raik, R.Ubar, H-D.Wuttke. Research Environment
for Teaching Digital Test. 49. Int. Conf.
IWK,
3. E.Ivask, A.Jutman,
E.Orasson, J.Raik, R.Ubar, H-D.Wuttke. Research Environment for Teaching
Digital Test. 49. Int. Conf. IWK,
Defect-Oriented
Testing of Digital Systems
Estonian-
Polish Joint Research Project (2003-2005)
The
goal of the joint research was to deal with two contradicting problems of
testing microelectronics systems: to
cope with the increasing complexities of systems based on deep-submicron technologies and to reach
high accuracy and reliability of testing. To solve these problems, a new
efficient hierarchical approach was developed to defect-oriented fault
simulation and test generation, based on a new uniform fault model [1]. To
reach high accuracy in simulating physical defects in deep-submicron
technologies, a new type of fault model and defect-oriented fault simulation
methods will be developed. The complexity of the problem will be handled by
raising the abstraction levels from gate to behavioral one by developing a new
uniform graph model. As the result of the joint research a novel type of
integrated circuit DefSim and a measurement environment for experimental study
of CMOS defects was created [2-5].
Joint
publications:
1. J.Raik,
R.Ubar, J.Sudbrock, W.Kuzmicz, W.Pleskacz. DOT: New Deterministic
Defect-Oriented ATPG Tool. Proc. of 10th IEEE European Test
Symposium, May 22-25, 2005, Tallinn, pp.96-101.
2.
W. Pleskacz, T. Borejko, A. Walkanis, V. Stopjakova, A. Jutman, R.Ubar,
"DefSim: CMOS Defects on Chip for Research and Education", in Proc.
of 7th IEEE Latin-American Test Workshop (LATW'06), Buenos Aires, Argentina,
Mar 26-29, 2006, pp. 74-79.
3.
A. Jutman, W. Pleskacz, "Study of Real CMOS Defects Using DefSim
Educational Environment", 9th Workshop on Design and Diagnostics of
Electronic Circuits and Systems (DDECS'2006), Prague, Czech Republic, April
18-21, 2006.
4.
W. Pleskacz, T. Borejko, A. Walkanis, V. Stopjakova, A. Jutman, R.
Ubar, "CMOS Defects Analysis using DefSim Measurement Environment",
in Informal Digest of Papers of 11th IEEE European Test Symposium
(ETS'06), Southampton, UK, May 21-25,
2006, pp. 241-246.
5.
http://defsim.testonica.com
Bilateral
German-Estonian project DILDIS (2002-2006)
Partner: Technical
An internet based training system was developed for teaching design and test in technical universities. The system allows to investigate design and test problems at lower logic level and higher RTL and microprogram levels, it can be used in classes, at home and during exams. The work was coordinated by FW V europroject REASON. A new BIST simulator started last year has been converted into an integrated analytic tool for research, engineering, and training. Now, the tool can handle different BIST generator types (LFSR, LFSR2, CA, GLFSR) and complex architectures (reseeding, hybrid, bit-flipping, etc.). The main feature of this tool is the possibility to compare properties and efficiency of these different approaches of pseudo-random pattern generation used in BIST. The tool has also necessary interfaces to be connected to ATI in-house test platform Turbo Tester.
Selected
publications:
1. R.Ubar, A.Jutman, E.Orasson, J.Raik, T.Evartson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. In the book ''Microelectronics Education'', Marcombo Boixareu Ed., 2002, pp.317-320.
2. A.Jutman, ASudnitson, R.Ubar, H.-D.Wuttke. E-Learning Environment in the Area of Digital Microelectronics. Proc. of the 5th Int. Conf. on Information Technology Based Higher Education and Training - ITHET 2004, Istambul, Turkey, 31 May – 2 June 2004, pp.278-283.
3. R.Ubar, A.Jutman, M.Kruus, E.Orasson, S.Devadze, H.-D.Wuttke. Learning Digital Test and Diagnostics via Internet. International Journal of Emerging Technologies in Learning. International Journal of Online Engineering, Vol.3, No.1, pp.1-9, 2007.
Teaching environment http://www.pld.ttu.ee/applets/
Functional Built-in Self-Test in Digital Systems
Bilateral German-Estonian project (2000-2002)
Partners: Fraunhofer
In this project we have investigated the main trends in the field of Functional Built-In Self-Testing (BIST) and we have developed a new BIST method based on the joint competences of the partners of the project. The new method exploits the functionality of the system under test itself. We investigated which extentions are needed to introduce into the Automated Test Pattern Generator (ATPG) to be used in developing this new BIST method. Some new features concerning the defect-orientation in test pattern generation have been investigated in [1,2] with the goal to increase the quality of tests to be generated.
Selected publications:
1. A.Schneider,
P.Schneider (FhG IIS/EAS
2.
2. E.Ivask, R.Ubar, J.Raik (TU Tallinn), A.Schneider (FhG
IIS/EAS
3.
3. R.Ubar, N.Mazurova, J.Smahtina, E.Orasson, J.Raik.
HyFBIST: Hybrid Functional Built-In Self-Test in Microprogrammed Data-Paths of
Digital Systems. Int. Conference MIXDES,
Reports http://www.pld.ttu.ee/~raiub/projektid/Bilat_Germ_00.pdf
Bilateral German-Estonian project DILDIS
(1999-2001)
Principal investigator: prof. R.Ubar
Partner:
A conception has been set up
how to combine learning, training and research phases in a laboratory course
for educating today’s VLSI and system
designers [1,2]. Then we developed a method and Java applets based software to
implement in the introductory phase of teaching interactive learning on the
basis of internet modules - “living pictures” [3,4]. Further on, the hands-on
training phase follows where commercial design tools and low-cost in-lab-made
test oriented tools are used for solving real engineering tasks with close
relationship to not yet solved research problems.
Publications:
1.
R.Ubar,
H.-D.Wuttke. Action Based Learning System for Teaching Digital Electronics and
Test. Proc. of 3rd European Workshop on Microelectronics Education,
Aix-en-Provence (France), May 18-19, 2000, pp.65-66.
2.
A.Sudnitsõn,
A.Levenko,D.Andrejev. JAVA-Based System for
3.
R.Ubar,
E.Orasson, D.Wuttke. Interactive Teaching Software “Introduction To Digital
Test”. 45th International
Conference, Ilmenau (
4.
R.Ubar,
E.Orasson, J.Raik, H.-D.Wuttke. Combining Learning, Training and Research in
Laboratory Course for Design and Test. 7th
Baltic Electronics Conference,
5.
R.Ubar,
H.-D.Wuttke. The DILDIS-Project – Using Applets for More Demonstrative Lectures
in Digital Systems Design and Test. Proceedings of the 31st ASEE/IEEE Frontiers
in Education Conference, FIE’2001, Oct. 10-13, 2001, Reno, NV, USA, pp.SIE-2-7.
Bilateral Swedish-Estonian project (1999-2000)
Design and
Test of Dependable Electronic Systems
Partner:
A new approach and the
implementation of several algorithms to speed up gate-level timing simulation
was proposed where instead of gate delays path delays for tree-like subcircuits
(macros) are used [1,3]. Therefore timing waveforms are calculated not for all
internal nodes of the gate-level circuit but only for outputs of macros. The
macros are represented by structurally synthesized binary decision diagrams
(SSBDD) which enable a fast computation of delays for macros. The new approach
to speed up the timing simulation is supported by encouraging experimental
results. A new hybrid BIST solution for testing systems-on-chip was developed
[2]. It combines pseudorandom test patterns with stored precomputed
deterministic test patterns. A method is proposed for finding an optimal
balance between pseudorandom and stored test patterns to perform core test with
minimum cost of both, time and memory, and without losing in test quality. To
speed up the optimization procedure, a method is proposed for approximate
estimation of the expected cost for different possible solutions with very low
computational overhead.
Publications:
1.
R.Ubar,
A.Jutman. Increasing the Speed of Delay
Simulation in Digital Circuits. 7th
Baltic Electronics Conference,
2.
G.Jervan,
Z.Peng, R.Ubar. Test Cost Minimization for Hybrid BIST IEEE. Int. Symp. on Defect and Fault Tolerance in
VLSI Systems.
3.
R.Ubar,
A.Jutman, Z.Peng. Improving the Efficiency of Timing Simulation in Digital
Circuits by Using Structurally Synthesized BDDs. IEEE 17th NORCHIP
Conference,
Generic VHDL Descriptions for BIST
Bilateral Swedish-Estonian project (1996-97)
Partner:
The goal of the project was
to develop generic synthesizable VHDL descriptions for including controlled
Built-In Self-Test (BIST) structures to digital designs. The approach is
referred to as Embedded Test Processors (ETP). The ETP architecture corresponds
to the IEEE Boundary-Scan standard 1149.1. In the implemented method, the
application of test patterns from an internal memory will be provided. For
measuring the quality of BIST and testability features of circuits, a set of
tools was developed [1,4]. With the goal of optimal BIST insertion, new
algorithms were developed for partitioning of digital systems [2].
Applications: The results were used in R&D projects of
Publications:
1.
G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. A Set
of Tools for Estimating Quality of Built-In Self-Test in Digital Circuits. Proc. of the International Symposium on
Signals, Circuits and Systems.
2.
H.Krupnova,
G.Saucier. Circuit Partitioning Method for FPGAs. Proceedings of the Estonian Acad. of Sci. Engng, 1997, Vol. 3 , No
4, pp. 280-291.
3.
R.Ubar,
J.Heinlaid, J.Raik, L.Raun. Calculation of Testability Measures on Structurally
Synthesized Binary Decision Diagrams. Proc.
of the 6th Baltic Electronics Conference, Oct. 7-9, 1998,
TEMPUS JEP
(1993 - 1995)
Partners: TU Darmstadt (
Defect-Oriented Testing of Digital Circuits
ESF Grant 5649 (2003-2006)
A
new conception for diagnostic modelling of digital systems was developed, which
allowed to create new more efficient methods for fault simulation and test
generation. The new scientific results achieved in the project can be listed as
follows: generalization of Binary Decision Diagrams as Generic Decision
Diagrams for diagnostic modelling of complex digital systems; new type of
functional fault model for mapping physical defects to logic level and for
formalizing hierarchical approach to testing of digital systems; new exact
critical path based reversive deductive fault analysis method, which the first
time allowed to carry out the parallel analysis of a set of test patterns and
to increase considerably the speed of test quality evaluation; new
defect-oriented test generation method, which made it possible the first time
to prove the redundancy of physical defects; new methods of test generation for
extended class of faults like shorts, delay faults and crosstalks; new more
efficient hierarchical test generation method for digital systems; test
generation method for a new type of digital systems – networks on chips for
testing dynamic as well as static faults.
To prove the efficiency of the developed new methods, a lot of software tools
were developed and integrated into a joint environment with the purpose to
improve the future research activities. One important part of this environment
- the Turbo Tester diagnostic package has been licenced already in more than
100 research labs all over the world. As a result of the project, 2 PhD thesis
and 13 MSc thesis were defended. The research was coordinated by 6
international joint projects, incl. two Framework 5 projects. In jointly
written 28 publications 23 coauthors are affiliated with 14 universities from 8
different countries. In total we published 55 papers incl. 2 monographies, 3
chapters in two monographies, 10 journal papers, and more than 40 conference
papers. During 2003-2006 we organized 8 international conferences.
Design Error Diagnosis in Digital Circuits and
Systems
ESF Grant 4003 (2000-2003)
A new conception to generate diagnostic tests and localize design errors in digital circuits was developed. The method is based on using the stuck-at fault model with subsequent translation of the diagnosis into the design error area. This allows to exploit standard gate-level test generators for verification and design error diagnosis purposes. Based on this conception, a new approach was proposed for removing design errors from digital circuits, which does not use any error model. To increase the efficiency of the verification of digital systems, new simulation methods were developed both, for the logic and higher register transfer level representations. The methods are based on the uniform model of decision diagrams which allowed to combine the multilevel simulation algorithms into a joint hierarchical simulation approach. As the result it was possible to increase the simulation speed compared to the traditional plane gate level simulation. New algorithms, methods and software were developed for test generation to increase the efficiency of verification and design error diagnosis procedures. A new conception was developed for defect-oriented test generation and fault simulation, based on the hierarchical handling of physical defects. A new problem of optimization of hybrid built-in self-test architectures was set up, and the algorithms and methods were developed to solve the problem. The results of the project are published in 59 refereed journal and conference papers. As the result of the project, 3 PhD and 6 magister thesis where defended.
Selected
publications:
1. Raik, J; Ubar, R. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000.
2. Jutman, A.; Ubar, R (2000). Design error diagnosis in digital circuits with stuck-at fault model. Microelectronics Reliability, 40(2), 307 - 320.
3. Cibakova, T.; Fischerova, M.; Gramatova, E.; Kuzmicz, W.; Pleskauz, WA.; Raik, J.; Ubar, R (2002). Hierarchical test generation for combinational circuits with real defects coverage. Microelectronics Reliability, 42(7), 1141 - 1149.
Digital Electronics Design & Test Virtual
Laboratory
ESF Grant 3658 (1999-2002)
The
main goal was to create a virtual internet based electronics design and test
laboratory, and to prove its vitality by increasing the efficiency of the
R&D work in design and test of digital circuits and systems. Originality
and novelty of the project idea is in creating a Web-based CAD environment in
the form of an international virtual laboratory. Investigations have been
carried out for possible solutions to create internet based design environment.
Corresponding networking software, web-server extensions and user-tools
interfaces have been developed. By using this environment cooperative
experimental researh has been carried out. New results have been obtained in
high-level test generation by increasing the efficiency of algorithms [1], and
by implementing the ideas of concurrency and genetics. A new method for design
error diagnosis in digital circuits that doesn’t use any error model was
developed [2]. For representing the information about erroneous signal paths in
the circuit, stuck-at fault model is used. This allows to adopt the methods and
tools of fault diagnosis used in hardware testing for using in design error
diagnosis. A new class of Decision Diagrams (DD), called Register-Oriented DDs
(RODD) has been introduced [3]. The model appeared to be an efficient and
compact representation of the system behavior for high-level cycle-based
simulation. In order to fully exploit the advantages of RODDs, new simulation
algorithms which are a combination of cycle-based forward event-driven and
recursive back-tracing techniques were proposed. The higher speed of simulation
in comparison with commercial tools was shown by cooperative experiments with
researchers from Fourier’ University in
Publications:
1. J.Raik,
R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit
Test Generation. Proc. of IEEE European Test Workshop,
2. 2. A.Jutman, R.Ubar. Design Error Diagnosis in Digital Circuits with Stuck-at Fault Model. Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.
3. 3.
R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in
High-Level Simulation with Decision Diagrams. Proc. of the IEEE ISCAS’2000
Conference,
Hierarchical methods for diagnostic analysis of
digital systems
ESF Grant 1850 (1996-1999)
As the result of the research in this project a novel diagnostic model for digital systems based on decision diagrams was developed. The new model the first time affords a joint representation of functions, structural features, faults, and transparency properties for the fault propagation. The advantages of the model are in the uniform formal handling of digital sytems on logical, procedural, functional as well as behavioral levels. Based on the universality of the model and on its different special properties, it became possible to develop several new efficient methods for test generation, fault simulation, fault localization, testability and fault tolerance estimation. The definition and usage of the class of structurally synthesized binary decision diagrams, as well as discovering several interesting properties of these diagrams afforded to increase significally the efficiency of several diagnostic algorithms.
The formalism
of decision diagrams in modeling of digital systems helped to simplify the
development of software for automatization of test and diagnostics. A new
automated test program generator
DECIDER for digital systems was developed, which is the one of the
fastest known analog in the field for a specific class of systems. A new
toolbox TURBO-TESTER for solving different test synthesis and analysis tasks
for digital circuits was developed, where differently from other similar
software, all tools are based on a single universal model library to give the
software the features like openness, simplicity and low-cost. TURBO-TESTER has
been and is being used at universities in
The results of the project are published in 43 papers during 1996-1999 in different journals and conference proceedings.
Experimental environment for innovative design
and scientific studies in digital
electronics
ESF Grant 2104 (1996-98)
The main result of the project is the
high-level technological environment at the Computer Engineering Department of
Tallinn Technical University for research, development and study in the field
of digital electronics and computer engineering. SYNOPSYS and CADENCE design
software, the original test software TURBO-TESTER, and a set of scripts, tools,
interfaces, converters and libraries created by this project serve as the basis
of this environment. The environment has been successfully tested in VLSI
design and in research in the field of digital test where during the last three
years about 60 papers has been published. The first estonian VLSI chip – a
cryptoprocessor (with complexity of about 200 thousand logic gates) has been
designed in the lab and manufactured in the West-Europe. The design class
allows to provide estonian students with education and training in the western
professional level, and serves as a basis for supporting engineering activities
in the field of electronics design in the Estonian industry.
Methods and Software for Testing Digital Systems
ESF Grant 574 (1993-95)
Theoretical
investigations based on the uniform alternative graphs approach for
generalizing methods for digital test synthesis at different system levels (at
logical, register transfer, procedural and behavioral levels) were carried out.
AGs serve as a mathematical basis for solving a wide spectrum of test design tasks, resulting in a uniform model and a restricted set of standardized procedures (horisontal universality). They also allow a uniform approach to test design at different system representation levels (vertical universality). Unlike the analogical binary decision diagrams (BDD) AGs support test design for gate-level structural faults (whereas BDDs help only getting functional tests with uncertain quality for the given implementation). AGs are not restricted for using at the logical level only. They allow also to represent fuctional and procedural descriptions of digital systems. Multilevel descriptions are easy to produce using the uniform graph language, since implementation details of functions given by labels at nodes in higher-level AGs can be represented by additional lower-level AGs.
On the mathematical basis of AGs, an
automated test design system TURBO-TESTER has been developed and experimented.
A set of test synthesis and analysis tools has been created and experimented.
Experimental data have shown the efficiency of new algorithms. TURBO-TESTER has
been introduced into the teaching process at the Technical University of
Tallinn and in several universities in
The results of the project are published in 28 papers and have been presented on 36 international conferences, workshops and seminars.
The project was supported by Estonian Science Foundation in 1993-1995.
Contract with
Artec Design - MIKROTEST (2001-2003)
The main goal of the project was the development of a new software for automatization of testing and fault diagnosis of digital systems, creation of new methods and tools for the development of self-test conception for digital systems, and the development and implementation of a new type of high quality self-testing microprocessor system. The partners of the project were Computer Engineering Department of TTU and Artec Design Group where the role of the first partner was creation of new tools for testing, the role of the second partner was the development of a new type of cryptographical network processor, and the result of the joint cooperation of both partners was a new methodology and conception for implementing self-testing paradigm in digital systems.
Selected
publications:
1. R.Ubar,
G.Jervan, Z.Peng, E.Orasson, R.Raidma. Fast Test Cost Calculation for Hybrid
BIST in Digital Systems. Proc. of EUROMICRO Symposium on Digital Systems
Design,
2.
2. G.Jervan, H.Kruus, Z.Peng, R.Ubar. About Cost
Optimization of Hybrid BIST in Digital Systems. 3rd IEEE Int. Symp. on Quality
of Electronic Design,
3.
3. J.Raik, E.Orasson, R.Ubar. Sequential Circuits BIST
with Status BIT Control. Int. Conference MIXDES,